Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Date 17/06/2021 00:00:00
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory Graphics Display Imaging Pin Strap General Purpose Input and Output (GPIO) PCH Electrical Specification CPU Electrical Specifications Global Device IDs CPU And Device IDs Audio, Voice, and Speech Connectivity Integrated (CNVi) PCI Express* (PCIe*) Universal Serial Bus (USB) Serial ATA (SATA) Flexible I/O Storage Serial Peripheral Interface (SPI) Intel® Serial I/O Generic SPI (GSPI) Controllers Enhanced Serial Peripheral Interface (eSPI) Real Time Clock (RTC) 8254 Timers High Precision Event Timer (HPET) Intel® LPSS Inter-Integrated Circuit (I2C) Controllers Host System Management Bus (SMBus) Controller System Management Interface and SMLink System Management Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Testability SoC Pin Location
Security Technologies Branch Monitoring Counters Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection (SMEP) Intel® Supervisor Mode Access Protection (SMAP) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID)
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation via SD3_RCOMP Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO (TIME_SYNC) GPIO Blink (BK) and Serial Blink (SBK) Interrupt / IRQ via GPIO Requirement Native Function and TERM Bit Setting Virtual GPIO (vGPIO)
DC Specifications Display Port* Specification HDMI* Specifications embedded Display Port* Specifications 16550 8-bit Addressing - Debug Driver Compatibility SVID AC Specifications MIPI* DSI Specification Memory Specifications MIPI* CSI Specifications CMOS DC Specifications GTL and Open Drain DC Specification PECI DC Characteristics
Features Supported Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single- Root I/O Virtualization (SR- IOV) SERR# Generation Hot-Plug PCI Express* Lane Polarity Inversion PCI Express* Controller Lane Reversal Precision Time Measurement (PTM)
Intel ® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This extension is primarily intended to increase processor addressability.
- Retains all key elements of compatibility to the xAPIC architecture:
- Delivery modes
- Interrupt and processor priorities
- Interrupt sources
- Interrupt destination types
- Provides extensions to scale processor addressability for both the logical and physical destination modes.
- Adds new features to enhance performance of interrupt delivery.
- Reduces complexity of logical destination mode interrupt delivery on link based architectures.
- Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations:
- In xAPIC compatibility mode, APIC registers are accessed through memory mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
- In x2APIC mode, APIC registers are accessed through Model Specific Register (MSR) interfaces. In this mode, the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery.
- Increased range of processor addressability in x2APIC mode:
- Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt processor addressability up to 4G-1 processors in physical destination mode. A processor implementation of x2APIC architecture can support fewer than 32-bits in a software transparent fashion.
- Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID within the cluster. Consequently, ((2^20) - 16) processors can be addressed in logical destination mode. Processor implementations can support fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic fashion.
- More efficient MSR interface to access APIC registers:
- To enhance inter-processor and self-directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR-based interfaces in x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in x2APIC mode.
- The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interrupts.
- The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for x2APIC mode.
- The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extensible for future Intel platform innovations.