Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1


ID 633935
Date 17/06/2021 00:00:00
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WAIT States from eSPI Slave

There are situations when the slave cannot predict the length of the command packet from the master (PCH). For non-posted transactions, the slave is allowed to respond with a limited number of WAIT states.

A WAIT state is a 1-byte response code. They must be the first set of response byte from the slave after the TAR cycles.