Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Datasheet
ID | Date | Version | Classification |
---|---|---|---|
633935 | 17/06/2021 00:00:00 | Public Content |
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Functional Description
The SD controller handles SD Protocol at transmission, packing data, adding cyclic redundancy check (CRC), start/end bit, and checking for transaction format correctness. The main use case for SD is to connect to an external detachable storage and /or I/O device. Both 1.8 V and 3.3 V signaling is supported. Additional information can be obtained from the specifications stated above.The following chart maps the working modes of SD.
SD Mode | Data Rate | Clock Frequency | Maximum Data Throughput |
---|---|---|---|
Default Speed/SDR12 | Single | 0 – 25 MHz | 12.5 MB/s |
High Speed/SDR25 | Single | 0 – 50 MHz | 25 MB/s |
SDR50 | Single | 0 – 100 MHz | 50 MB/s |
DDR50 | Dual | 0 – 50 MHz | 50 MB/s |
SDR104 | Single | 0 – 208 MHz | 104 MB/s |