Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
From the platform perspective, the FIVRs require an input rail to generate the internal voltage rails. This rail is referred to as VCCIN_AUX.For the PCH, the input regulator must be able to support at least 1.8 V. During the deep S0ix states, the input rail to the FIVRs can be disabled. This will be done by driving the CORE_VID values to ‘00. VCCIN_AUX powergood during initial reset is tied into the PMC_RSMRST_N signal, requiring that the FIVR input voltage rail is stable in the same window as the other PMC_SLP_SUS_N rails. Internal FIVRs will generate Vnn, V1P05 rails.