Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

Interrupts

UART interface has an interrupt line which is used to notify the driver that service is required.

When an interrupt occurs, the device driver needs to read both the host controller and DMA status and TX completion interrupt registers to identify the interrupt source. Clearing the interrupt is done with the corresponding interrupt register in the host controller or DMA.

All interrupts are active high and their behavior is level interrupt.