Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

Reset

Each host controller has an independent rest associated with it. Control of these resets is accessed through the Reset Register.

Each host controller and DMA will be in reset state once powered off and require SW (BIOS or driver) to write into specific reset register to bring the controller from reset state into operational mode.