Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Datasheet
| ID | Date | Version | Classification |
|---|---|---|---|
| 633935 | 17/06/2021 00:00:00 | Public Content |
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Platform PU/PD Requirements
| I/F | Signals | PU/PD in Platform | Comments |
|---|---|---|---|
| BRI/RGI Bluetooth* UART | CNV_RGI_DT | PU (20kohm) | This pull is required so that the SOC will be able to reliably detect that the CRF is present at power-up. However, it is possible to increase the resistor to 50K or even to to 100K instead of 20K. |
| Init signals | RF_RESET_N | PD (75kohm) | It is highly encouraged to increase this resistor (or allow to switch it off when CNVi is active; not sure this is possible at the platform level). This resistor consumes power (43uW) all the time. This recommendation applicable only for reset muxed with GP_F04 |
| A4WP indication | A4WP_PRESENT | PD (75kohm) | Native function A4WP is not supported. The pin can instead be used as GPIO (when BIOS programs the pin to GPIO functionality). It is recommended to have an external pull down on the pin regardless of the pin being used or not to minimize power consumption. If the pin is used as GPIO, there should NOT be any on-board device driving the pin high until BIOS programs it to GPIO functionality. |