Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
SVID AC Specifications
|T # Parameter||Minimum||Typ||Maximum||Unit||Notes|
|Tco CPU clock to data delay||1.2||-||9.6||ns||-|
|Tsu_CPU - Setup time of signal VDIO at CPU side||1||-||-||ns||3, 4|
|Thld_CPU - hold time of signal VDIO at CPU side||3||-||-||ns||3, 4|
|VCLK Rise Time||0.1||-||5.5||ns||3|
|VCLK Fall Time||0.1||-||5.5||ns||3|
1. Period and duty cycle are measured with respect to 0.5 * VTT.
2. High and low time is measured with respect to 0.5 * VTT.
3. Rise and Fall times are measured from 0.45 V and 0.65 V.
4. Tperiod, Thigh, Tlow and Duty Cycle variation as a result of internal CPU Clock logic only. Additional variation may be introduced as a result of the Clock MB topology (like different Rpu values or MB impedance).