Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

Signal Description

Name

Type

Description

GPIO Fixed Function

GP_​H11/AVS_​I2S2_​SCLK

I/O

For CNVi: Unused

For standard CNV with UART host support: Optional Bluetooth I2S bus clock

GP_​H12/AVS_​I2S2_​SFRM/CNV_​RF_​RESET_​N

I/O

For CNVi: RF companion (CRF) reset signal, active low. Require a 75KOhm Pull-Down on platform/motherboard level. Recommended not use it for bootstrapping during early Platform init flows.

For standard CNV with UART host support: Optional Bluetooth I2S bus sync

GP_​H13/AVS_​I2S2_​TXD/MODEM_​CLKREQ

O

For CNVi: Clock request signal. Used to request the RF companion clock (38.4M Ref clock); In PCH this function is not used, BUT this signal is also used for CNVi Init flow, so it must be connected on platform level even when clk sharing ability is not used/feasible.

PCH is using internal clk (38.4 MHz clk) and NOT taking this clk from the CRF (as was optional in previous generations)

For standard CNV with UART host Bluetooth* support: Optional Bluetooth* I2S bus data output (input to BT module).

GP_​H14/AVS_​I2S2_​RXD

I

For CNVi: Unused.

For standard CNV with UART host support: Optional Bluetooth* I2S bus data output (input to BT module)

GP_​E20/CNV_​BRI_​DT

O

For CNVi: BRI bus TX.

For standard CNV CNV with UART host support: BT UART RTS#

Note:

Require a 100-50-20KOhm (any of) Pull-up on platform/motherboard level. Recommended not use it for bootstrapping during early Platform init flows

GP_​E21/CNV_​BRI_​RSP

I

For CNVi: BRI bus RX.

For standard CNV CNV with UART host support: BT UART RXD

GP_​E22/CNV_​RGI_​DT

O

For CNVi: RGI bus TX.

For standard CNV with UART host support: BT UART TXD

GP_​E23/CNV_​RGI_​RSP

I

For CNVi: RGI bus RX.

For standard CNV with UART host support: BT UART CTS#

GP_​H01/SD_​SDIO_​PWR_​EN_​N/CNV_​RF_​RESET_​N

O

For CNVi (main): RF companion (CRF) reset signal, active low. Require a 75KOhm Pull-Down on platform/motherboard level. Recommended not use it for bootstrapping during early Platform Init flows.

GP_​H02/MODEM_​CLKREQ

O

For CNVi(main): Clock request signal. Used to request the RF companion clock (38.4M Ref clock); In PCH this function is not used, BUT this signal is also used for CNVi Init flow, so it must be connected on platform level even when clk sharing ability is not used/feasible. PCH using internal clk (38.4 MHz clk) and NOT taking this clk from the CRF (as was optional in previous generations)

GP_​D21/CNV_​PA_​BLANKING

I

For CNVi and standard CNV: Optional WLAN/BT-WWAN coexistence signal COEX3. Used to be co-existence signal for external GNSS solution

GP_​D19/CNV_​MFUART2_​RXD

I/O

For CNVi and standard CNV: Optional WLAN/BT-WWAN coexistence signal COEX (Input)

GP_​D20/CNV_​MFUART2_​TXD

I/O

For CNVi and standard CNV: Optional WLAN/BT-WWAN coexistence signal COEX (Output)

Fixed Special Purpose I/O

CNV_​WT_​CLKP

O

CNVio bus TX CLK+

CNV_​WT_​CLKN

O

CNVio bus TX CLK-

CNV_​WT_​D0P

O

CNVio bus Lane 0 TX+

CNV_​WT_​D0N

O

CNVio bus Lane 0 TX-

CNV_​WT_​D1P

O

CNVio bus Lane 1 TX+

CNV_​WT_​D1N

O

CNVio bus Lane 1 TX-

CNV_​WR_​CLKP

I

CNVio bus RX CLK+

CNV_​WR_​CLKN

I

CNVio bus RX CLK-

CNV_​WR_​D0P

I

CNVio bus Lane 0 RX+

CNV_​WR_​D0N

I

CNVio bus Lane 0 RX-

CNV_​WR_​D1P

I

CNVio bus Lane 1 RX+

CNV_​WR_​D1N

I

CNVio bus Lane 1 RX-

CNV_​WT_​RCOMP

O

WiFi DPHY RCOMP, analog connection point for an external bias resistor to ground

Selectable Special Purpose I/O

USB2P_​8

Bluetooth USB host bus (positive) for standard CNV. Optional to connect to a Bluetooth USB+ pin on the Bluetooth module. Port 8 is the recommended port .

USB2N_​8

Bluetooth USB host bus (negative) for standard CNV. Optional to connect to a Bluetooth USB- pin on the Bluetooth module. Port 8 is the recommended port.

W_​disable1#(GPIO)

I

Used for Wi-Fi* RF-Kill control.

This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init).

W_​disable2#(GPIO)

I

Used for BT RF-Kill control.

This pin can be connected to a platform switch or to SoC GPIOs (recommendation- if possible do not use GPIOs that have Platform impact as “bootstraps” during platform init).