Pin Strap

Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID	Date	Version	Classification
633935	17/06/2021 00:00:00		Public Content

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The following signals are used for static configuration. They are sampled at the rising edge of PMC_DSW_PWROK, PMC_RSMRST_N, or PMC_PCH_PWROK to select configuration and then revert later to their normal usage. To invoke the associated mode, the signal should meet both set up and hold time of 1us, with respect to the rising edge of the sampling signal.

Pin Straps

Signal	Usage	When Sampled	Comment
GP_C01	Top Swap Override	Rising edge of PMC_PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0 = Disable “Top Swap” mode. (Default) 1 = Enable “Top Swap” mode. This inverts an address on access to SPI and firmware hub, so the processor believes it fetches the alternate boot block instead of the original boot-block. PCH will invert A16 (default) for cycles going to the upper two 64-KB blocks in the FWH or the appropriate address lines (A16, A17, or A18) as selected in Top Swap Block size soft strap. Notes: The internal pull-down is disabled after PCH_PWROK is high. Software will not be able to clear the Top Swap bit until the system is rebooted. The status of this strap is readable using the Top Swap bit (Bus0, Device31, Function0, offset DCh, bit4). This signal is in the primary well.
GP_C02	No Reboot	Rising edge of PMC_PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0 = Disable “No Reboot” mode. (Default) 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GP_C08/UART0_RXD	TLS Confidentiality	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-down. 0 = Disable Intel^® CSE Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default) 1 = Enable Intel^® CSE Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Notes: The internal pull-down is disabled after PMC_RSMRST_N de-asserts. This signal is in the primary well.
GP_C09/UART0_TXD	eSPI Disable	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-down. 0 = Enable eSPI. (Default) 1 = Disable eSPI. Notes: The internal pull-down is disabled after PMC_RSMRST_N de-asserts. This signal is in the primary well.
GP_C10/UART0_RTS_N	Reserved	Rising edge of PMC_RSMRST_N	External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling. There is no internal termination.
GP_C13/UART1_TXD	CPUNSSC Clock Frequency	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-down. 0 = 38.4 MHz clock (direct from crystal) (default) 1 = 19.2 MHz clock (derived from 38.4 MHz crystal) Notes: The internal pull-down is disabled after PMC_RSMRST_N de-asserts. When used as PCHHOT# and strap low, a 150 K pull-up is needed to ensure it does not override the internal pull-down strap sampling. This signal is in the primary well.
GP_D08/SIO_SPI2_CS0_N/UART0A_RXD	Reserved	Rising edge of PMC_RSMRST_N	External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling. There is no internal termination.
GP_D09/SIO_SPI2_CLK/SIO_UART0A_TXD	Reserved	Rising edge of PMC_RSMRST_N	External pull-up is required. Recommend 100 K if pulled up to 3.3 V or 75 K if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling. There is no internal termination.
GP_A15	Flash Descriptor Security Override	Rising edge of PMC_PCH_PWROK	This strap has a 20 kohm ± 30% internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. (Default) 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external Pull-up in manufacturing/debug environments ONLY. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GP_E06/IMGCLKOUT_3	Reserved	Rising edge of PMC_RSMRST_N	External pull-up is required. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling. There is no internal termination.
GP_E14/DDI0_DDC_SDA	Used for BSSB_LS0(1.8V) or the display GMBus(3.3V)	Rising edge of PMC_RSMRST_N	This strap has 20 K internal pull-down. 0 = GP_E13/GP_E14 pins at 1.8 V 1 = GP_E13/GP_E14 pins at 3.3 V Note:This signal is in the primary well.
GP_E16/DDI1_DDC_SDA	Used for BSSB_LS1(1.8V) or the display GMBus(3.3V)	Rising edge of PMC_RSMRST_N	This strap has 20 K internal pull-down. 0 = GP_E15/GP_E16 pins at 1.8 V 1 = GP_E15/GP_E16 pins at 3.3 V Note:This signal is in the primary well.
GP_E18/DDI2_DDC_SDA	Used for BSSB_LS2(1.8V) or the display GMBus(3.3V)	Rising edge of PMC_RSMRST_N	This strap has 20 K internal pull-down. 0 =GP_E17/GP_E18 pins at 1.8 V 1 = GP_E17/GP_E18 pins at 3.3 V Note:This signal is in the primary well.
GP_E12/IMGCLKOUT_4	Used for BSSB_LS3(1.8V) or the display GMBus(3.3V)	Rising edge of PMC_RSMRST_N	This strap has 20 K internal pull-down. 0 = GP_E11/GP_E12 pins at 1.8 V 1 = GP_E11/GP_E12 pins at 3.3 V Note:This signal is in the primary well.
GP_D10	RSVD	Rising edge of PMC_RSMRST_N	This strap has 20 K internal pull-down. Do not pull this pin high on board.
DBG_PMODE	Reserved	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-up. This strap should sample high. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-up is disabled after PMC_RSMRST_N de-asserts. This signal is in the primary well.
GP_DSW07	Reserved	Rising edge of PMC_DSW_PWROK	This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-down is disabled after DSW_PWROK is high. This signal is in the DSW well.
GP_E00/IMGCLKOUT_0	XTAL Frequency Selection	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-down. This strap should not be pulled high since 24 MHz crystal is not supported on the PCH. 0 = 38.4 MHz/19.2 MHz(default) 1 = 24 MHz Notes: The internal pull-down is disabled after PMC_RSMRST_N de-asserts. This signal is in the primary well.
GP_E22/CNV_RGI_DT	M.2 CNVi Mode Select	Rising edge of PMC_RSMRST_N	A weak external pull-up is required. 0 = Integrated CNVi enabled. 1 = Integrated CNVi disabled. Note:When a RF companion chip is connected to the PCH CNVi interface. There is no internal termination.
GP_D11/SPI2_MOSI/UART0A_CTS_N	eSPI Flash Sharing Mode	Rising edge of PMC_RSMRST_N	This strap has a 20 kohm ± 30% internal pull-down. 0 = Master Attached Flash Sharing (MAFS) is enabled. (Default) 1 = Slave Attached Flash Sharing (SAFS) is enabled. Notes: The internal pull-down is disabled after PMC_RSMRST_N de-asserts. This signal is in the primary well.
INTRUDER_N²	SPI Voltage Configuration	SRTCRST_N	There is no internal pull-up or pull-down on the signal. An external pull-up / pull-down is required. 0 = SPI operation voltage is 3.3 V (10 kohm pull-down to GND) 1 = SPI operation voltage is 1.8 V (1 Mohm pull-up to VCCRTC)
CFG_00	EAR	-	1 = (Default) Normal Operation;. 0 = Reserved.
CFG_04	eDP Presense	-	Embedded Display Port Presence Strap 1= (default) disabled. 0=enabled.

Notes:

CFG signals have a default value as ‘1’.

INTRUDER_N is exclusively used for SPI Voltage Configuration. Chassis Intrusion Detection is not supported.