Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Datasheet
Signal Description
Name | Type | Description |
---|---|---|
Intel® High Definition Audio Signals | ||
GP_R04/HDA_RST_N | O | Intel® HD Audio Reset: Master H/W reset to internal/external codecs. |
GP_R01/HDA_SYNC/AVS_I2S0_SFRM | O | Intel® HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. Also used to encode the stream number. |
GP_R00/HDA_BCLK/AVS_I2S0_SCLK | O | Intel® HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel® HD Audio controller. |
GP_R02/HDA_SDO/AVS_I2S0_TXD | O | Intel® HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. |
GP_R03/HDA_SDI0/AVS_I2S0_RXD | I | Intel® HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
GP_R05/HDA_SDI1/AVS_I2S1_RXD | I | Intel® HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
I2S/PCM Interface | ||
GP_R00/HDA_BCLK/AVS_I2S0_SCLK | I/O | I2S/PCM serial bit clock 0: Clock used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_H15/AVS_I2S1_SCLK | I/O | I2S/PCM serial bit clock 1: This clock is used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_H11/AVS_I2S2_SCLK | I/O | I2S/PCM serial bit clock 2: This clock is used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_R01/HDA_SYNC/AVS_I2S0_SFRM | I/O | I2S/PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_R06/AVS_I2S1_SFRM | I/O | I2S/PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_H12/AVS_I2S2_SFRM/CNV_RF_RESET_N | I/O | I2S/PCM serial frame indicator 2: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode). |
GP_R02/HDA_SDO/AVS_I2S0_TXD | O | I2S/PCM transmit data (serial data out)0: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GP_R07/AVS_I2S1_TXD | O | I2S/PCM transmit data (serial data out)1: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GP_H13/AVS_I2S2_TXD/MODEM_CLKREQ | O | I2S/PCM transmit data (serial data out)2: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GP_R03/HDA_SDI0/AVS_I2S0_RXD | I | I2S/PCM receive data (serial data in)0: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GP_R05/HDA_SDI1/AVS_I2S1_RXD | I | I2S/PCM receive data (serial data in)1: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GP_H14/AVS_I2S2_RXD | I | I2S/PCM receive data (serial data in)2: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GP_D18/AVS_I2S_MCLK | O | I2S/PCM Master reference clock: This signal is the master reference clock that connects to an audio codec. |
DMIC Interface | ||
GP_S06/DMIC_CLK_0 | O | Digital Mic Clock: Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. |
GP_S02/DMIC_CLK_1 | O | Digital Mic Clock: Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. |
GP_S07/DMIC_DATA_0 | I | Digital Mic Data: Serial data input from the digital mic. |
GP_S03/DMIC_DATA_1 | I | Digital Mic Data: Serial data input from the digital mic. |
SoundWire* Interface | ||
GP_S04/SNDW1_CLK | I/O | SoundWire* Clock: Serial data clock to external peripheral devices. |
GP_S05/SNDW1_DATA | I/O | SoundWire* Data: Serial data input from external peripheral devices. |