Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset3

Immediately After Reset3

S3/S4/S5

Deep Sx

SATA_​[1:0]_​TXP/N, SATA_​[1:0]_​RXP/N3

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

SATA_​LED_​N

Primary

Undriven

Undriven

Undriven

OFF

SATA_​[1:0]_​DEVSLP

Primary

Undriven

Undriven

Driven Low

OFF

SATA_​0_​GP

Primary

Undriven

Undriven

Undriven

OFF

  1. Pin defaults to GPIO mode. The pin state during and immediately after reset follows default GPIO mode pin state. The pin state for S0 to Deep Sx reflects assumption that GPIO Use Select register was programmed to native mode functionality. If GPIO Use Select register is programmed to GPIO mode, refer to Multiplexed GPIO (Defaults to GPIO Mode) section for the respective pin states in S0 to Deep Sx.
  2. Reset reference for primary well pins is PMC_​RSMRST_​N.