Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

Interrupt Levels

Interrupts directed to the internal 8259s are active high. If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with legacy interrupts. They may be shared although it is unlikely for the operating system to attempt to do this.

If more than one timer is configured to share the same IRQ (using the TIMERn_​INT_​ROUT_​CNF fields), then the software must configure the timers to level-triggered mode. Edge-triggered interrupts cannot be shared.