The processor supports C0, C2, C3, C6, C7, C8, and C10 package states.
The following is a summary of the general rules for package C-state entry. These apply to all package C-states, unless specified otherwise:
A package C-state request is determined by the lowest numerical processor IA core C-state amongst all processor IA cores and also the module C-state.
A package C-state is automatically resolved by the processor depending on the processor IA core idle power states and the status of the platform components.
Each processor IA core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state.
The platform may allow additional power savings to be realized in the processor.
For package C-states, the processor is not required to enter C0 before entering any other C-state.
Entry into a package C-state may be subject to auto-demotion – that is, the processor may keep the package in a deeper package C-state then requested by the operating system if the processor determines, using heuristics, that the deeper C-state results in better power/performance.
The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following:
If a processor IA core break event is received, the target processor IA core is activated and the break event message is forwarded to the target processor IA core.
If the break event is not masked, the target processor IA core enters the processor IA core C0 state and the processor enters package C0.
If the break event is masked, the processor attempts to re-enter its previous package state.
If the break event was due to a memory access or snoop request,
But the platform did not request to keep the processor in a higher package C-state, the package returns to its previous C-state.
And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state.
The package level C states C3 through C10 are entered and exited through the C2R state.
Package C State
Processor active state
Cannot be requested explicitly by the software.
All processor IA cores in C6 or deeper + Processor Graphic cores in RC6, memory path may be open.
The processor will enter Package C2 when:
Transitioning from Package C0 to deep Package C state or from deep Package C state to Package C0.
All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but there are constraints (LTR, programmed timer events in the near future and so forth) that prevent entry to any state deeper than C2 state.
All IA cores requested C6 or deeper + Processor Graphic cores in RC6 but a device memory access request is received. Upon completion of all outstanding memory requests, the processor transitions back into a deeper package C-state.
A transitional package C-State
All cores in C6 or deeper + Processor Graphics in RC6, LLC may be flushed and turned off, memory in self refresh, memory clock stopped.
The processor will enter Package C3 when:
All IA cores in C6 or deeper + Processor Graphic cores in RC6.
The platform components/devices allows proper LTR for entering Package C3.
Package C3 + BCLK is off + IMVP VRs voltage reduction/PSx state is possible.
The processor will enter Package C6 when:
All IA cores in C6 or deeper + Processor Graphic cores in RC6.
The platform components/devices allow proper LTR for entering Package C6.
Package C6 + If all IA cores requested C7, LLC ways may be flushed until it is cleared. If the entire LLC is flushed, voltage will be removed from the LLC.
The processor will enter Package C7 when:
All IA cores in C7 or deeper + Processor Graphic cores in RC6.
The platform components/devices allow proper LTR for entering Package C7.
Package C6 + If all IA cores requested C7S, LLC is flushed in a single step, voltage will be removed from the LLC.
The processor will enter Package C7S when:
All IA cores in C7S or deeper + Processor Graphic cores in RC6.
The platform components/devices allow proper LTR for entering Package C7S.
Package C7 + LLC should be flushed at once.
The processor will enter Package C8 when:
All IA cores in C8 or deeper + Processor Graphic cores in RC6.
The platform components/devices allow proper LTR for entering Package C8.
All processor die VR's are in lowest PS state or LPM + 38.4 MHz clock off.
The processor will enter Package C10 when:
All IA cores in C10 + Processor Graphic cores in RC6.
The platform components/devices allow proper LTR for entering Package C10.
Package C-State Auto-Demotion
The Processor may demote the Package C-state(s) to a shallower C-state(s), for example instead of going into package C10, it will demote to package C8 (and so on as required). The processor decision to demote the package C-state is based on the required C-states latencies, entry/exit energy/power and devices LTR.
Processor supports the following S0ix variants. As the system goes deeper into S0ix, the overall functionality reduces, thereby, reducing the total power consumption. Longer S0ix residency gives better battery performance for a mobile/hand-held device.
Modern Standby is a relevant platform state in Windows*. Other relevant S0ix states exist on other OS. On display time out, the OS requests the processor to enter the package C10 state and platform devices at RTD3 (or disabled) in order to attain low power in idle. Relevant S0ix states require proper BIOS and OS configuration.
S0ix Power States
CPU Package State
System Power States
Fully running S0 with aggressive opportunistic power management actions
OPI L1 and PLL shutdown Individual PLL shutdown 1 Internal power gating of PCH controllers 2 Internal HSIO per lane power gating
Pervasively Idle S0 and Root PLLs are off
C6 or deeper
All actions from LP1 + Gen 2 PLL/BCLK PLL shutdown
All actions from LP2 + XTAL shutdown SLP_S0# VCCPRIM_CORE Low Voltage Mode
Individual PLL shutdown - Each I/O interface when becoming sufficiently idle (typically requiring a minimum link power state) can have its respective I/O PLL be shutdown dynamically. This includes PCIe Gen3, SATA, USB 2.0 and MIPI.
Internal Power Gating of PCH controllers - Each host controller (that is, xHCI, AHCI), PCIe* root port or embedded subsystem (Intel® CSE, Audio) when becoming sufficiently idle can autonomously power gate its core digital logic and local memory arrays. xHCI power gating is on a per port basis.