Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Date 17/06/2021 00:00:00
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Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory Graphics Display Imaging Pin Strap General Purpose Input and Output (GPIO) PCH Electrical Specification CPU Electrical Specifications Global Device IDs CPU And Device IDs Audio, Voice, and Speech Connectivity Integrated (CNVi) PCI Express* (PCIe*) Universal Serial Bus (USB) Serial ATA (SATA) Flexible I/O Storage Serial Peripheral Interface (SPI) Intel® Serial I/O Generic SPI (GSPI) Controllers Enhanced Serial Peripheral Interface (eSPI) Real Time Clock (RTC) 8254 Timers High Precision Event Timer (HPET) Intel® LPSS Inter-Integrated Circuit (I2C) Controllers Host System Management Bus (SMBus) Controller System Management Interface and SMLink System Management Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Testability SoC Pin Location
Security Technologies Branch Monitoring Counters Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection (SMEP) Intel® Supervisor Mode Access Protection (SMAP) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID)
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation via SD3_RCOMP Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO (TIME_SYNC) GPIO Blink (BK) and Serial Blink (SBK) Interrupt / IRQ via GPIO Requirement Native Function and TERM Bit Setting Virtual GPIO (vGPIO)
DC Specifications Display Port* Specification HDMI* Specifications embedded Display Port* Specifications 16550 8-bit Addressing - Debug Driver Compatibility SVID AC Specifications MIPI* DSI Specification Memory Specifications MIPI* CSI Specifications CMOS DC Specifications GTL and Open Drain DC Specification PECI DC Characteristics
Features Supported Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single- Root I/O Virtualization (SR- IOV) SERR# Generation Hot-Plug PCI Express* Lane Polarity Inversion PCI Express* Controller Lane Reversal Precision Time Measurement (PTM)
Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters—a simple read operation, counter Latch command, and the Read-Back command. Each is explained below.
With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them.