Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1
Datasheet
Processor IA Core C-State Rules
The following are general rules for all processor IA core C-states, unless specified otherwise:
- A processor IA core transitions to C0 state when:
- Any interrupt coming into the processor package may wake any processor IA core.
- A system reset re-initializes all processor IA cores.
Core C-State | C-State Request Instruction | Description |
---|---|---|
C0 | N/A | The normal operating state of a processor IA core where code is being executed |
C1 | MWAIT(C1) | AutoHalt - core execution stopped, autonomous clock gating (package in C0 state) |
C1E | MWAIT(C1E) | Core C1 + lowest frequency and voltage operating point (package in C0 state) |
C6 | MWAIT(C6) | C6: Halt execution, flush core caches, flush core state, stop clock distribution, turn core voltage off |
C6S | MWAIT(C6S) | C6S: C6 + allow entry to MC6 |
C7-C8 | MWAIT(C7/C8) | Same as C6S, shrink the LLC |
C10 | MWAIT(C10) | Same as C6S, LLC flushed. Enable S0ix |
Core C-State Auto-Demotion
In general, deeper C-states, such as C6, have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on battery life and idle power. To increase residency and improve battery life and idle power in deeper C-states, the processor supports C-state auto-demotion.
The decision to demote a processor IA core from C6 to C1/C1E is based on each processor IA core’s immediate residency history. Upon each processor IA core C6 request, the processor IA core C-state is demoted to C1 until a sufficient amount of residency has been established. At that point, a processor IA core is allowed to go into C6. If the interrupt rate experienced on a processor IA core is high and the processor IA core is rarely in a deep C-state between such interrupts, the processor IA core can be demoted to a C1 state.
This feature is disabled by default. Refer the Firmware Architecture Specifications for more details on how to enable this.
There are also Module C-states related to the core C states.
Module C-State | Description |
---|---|
MC0 | At least one core in C0 |
MC6 | All cores in C6 (powered off) CPLL bypassed (powered off) L2 flushed, L2 voltage = powered off |