Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset1

S3/S4/S5

Deep Sx

SML_​DATA0

Primary

Undriven

Undriven

Undriven

Undriven

SML_​CLK0

Primary

Undriven

Undriven

Undriven

Undriven

Notes:
  1. Reset reference for primary well pins is PMC_​RSMRST_​N.