Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents
DSP

AC Characteristics

PCI Express* Interface Timings

Symbol

Parameter

Minimum

Maximum

Unit

Figures

Notes

Transmitter and Receiver Timings

UI (Gen1)

Unit Interval – PCI Express

399.88

400.12

ps

5

UI (Gen 2)

Unit Interval – PCI Express

199.9

200.1

ps

5

UI (GEN3)

Unit Interval – PCI Express

124.96

125.03

ps

TTX-EYE (Gen 1/Gen 2)

Minimum Transmission Eye Width

0.75

UI

Figure: PCI Express* Transmitter Eye

1,2

TTX-EYE-MEDIAN-to-MAX-JITTER (Gen 1)

Maximum time between the jitter median and maximum deviation from the median

0.125

UI

1,2

TRX-EYE (Gen 1)

Minimum Receiver Eye Width

0.4

UI

Figure: PCI Express* Receiver Eye

3,4

TRX-EYE (Gen 2)

Minimum Receiver Eye Width

0.6

UI

3,4

Notes:
  1. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs. (also refer to the Transmitter compliance eye diagram)
  2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value.
  3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
  4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
  5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.

PCI Express* Transmitter Eye

Note:Gen1 example is shown for the illustration. Refer to www.pcisig.com for the updated specifications.

PCI Express* Receiver Eye

Note:Gen1 example is shown for the illustration. Refer to www.pcisig.com for the updated specifications.

DDC Characteristics 

Signal Group: eDP_​VDDEN, eDP_​BKLTEN, eDP_​BKLTCTL, DDI[0:2]_​CTRLCLK, DDI[0:2]_​CTRLDATA

Symbol

Parameter

Standard Mode

Fast Mode

1 MHz

Units

Maximum

Minimum

Maximum

Minimum

Maximum

Fscl

Operating Frequency

100

0

400

0

1000

kHz

Tr

Rise Time1

1000

20+0.1Cb2

300

120

ns

Tf

Fall Time1

300

20+0.1Cb2

300

120

ns

Notes:
  1. Measurement Point for Rise and Fall time: VIL(max)–VIH(min)
  2. Cb = total capacitance of one bus line in pF. If mixed with High-speed mode devices, faster fall times according to High-Speed mode Tr/Tf are allowed.