Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset2

Immediately After Reset2

S3/S4/S5

Deep Sx

High Definition Audio Interface

HDA_​RST_​N

Primary

Driven Low

Driven Low

Driven Low

OFF

HDA_​SYNC

Primary

Internal Pull-down

Driven Low

Internal Pull-down

OFF

HDA_​BLK

Primary

Driven Low

Driven Low

Driven Low

OFF

HDA_​SDO

Primary

Internal Pull-down

Driven Low

Internal Pull-down

OFF

HDA_​SDI[1:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

I2S/PCM Interface

AVS_​I2S[2:1]_​SCLK

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

AVS_​I2S[2:0]_​SFRM

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

AVS_​I2S0_​TXD

Primary

Internal Pull-down

Driven Low

Low then disabled (Refer Note)

OFF

AVS_​I2S[2:1]_​TXD

Primary

Driven Low

Driven Low

Driven Low

OFF

AVS_​I2S[2:0]_​RXD

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

AVS_​I2S_​MCLK

Primary

Driven Low

Driven Low

Driven Low

OFF

DMIC Interface

DMIC_​CLK[1:0]

Primary

Driven Low

Driven Low

Driven Low

OFF

DMIC_​DATA[1:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

SoundWire* Interface

SNDW1_​DATA

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

OFF

SNDW_​CLK1

Primary

Driven Low

Driven Low

Driven Low

OFF

Notes:
  1. I2S0_​TXD are straps in which the pull-down only occurs during the sampling window and then the pull-ups are disabled.
  2. Reset reference for primary well pins is PMC_​RSMRST_​N.