Intel® Pentium® Silver and Intel® Celeron® Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 633935 | 12/27/2022 | Public |
Interrupt Generation
The root port generates interrupts on behalf of hot-plug, power management, link bandwidth management, Link Equalization Request and link error events, when enabled. These interrupts can either be pin-based, or can be Message Signal Interrupt (MSI), when enabled.
When an interrupt is generated using the legacy pin, the pin is internally routed to the SoC interrupt controllers. The pin that is driven is based upon the setting of the STRPFUSECFG.PXIP configuration registers.
Below table summarizes interrupt behavior for MSI and wire-modes. In the table “bits” refers to the hot-plug and PME interrupt bits.
| Interrupt Register | Wire-Mode Action | MSI Action |
|---|---|---|
| All bits 0 | Wire inactive | No action |
| One or more bits set to 1 | Wire active | Send message |
| One or more bits set to 1, new bit gets set to 1 | Wire active | Send message |
| One or more bits set to 1, software clears some (but not all) bits | Wire active | Send message |
| One or more bits set to 1, software clears all bits | Wire inactive | No action |
| Software clears one or more bits, and one or more bits are set on the same clock | Wire active | Send message |