Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents

USB 3.2 Hosting DCI.DBC

It relies on Debug Class Devices (DbC) which is comprised of a set of logic that is bolted to the side of the xHCI host controller and enable the target to act the role of a USB 3.2 device for debug purpose. This path uses the USB 3.2 packet protocol layer, USB 3.2 link layer flow control and USB 3.2 physical layer at 5 GHz. DCI.DBC - fast speed. USB 3.2 only works in S0. USB 2.0 survives S0ix and Sx states and provides early boot access.