Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents


When PECI Over eSPI is enabled, the eSPI device (i.e. EC) can access the processor PECI interface via eSPI controller.

The PECI bus may be connected to the PCH via the eSPI interface. The operation over eSPI is selected via a soft strap.

PECI over eSPI is not supported in Sx state. The connected eSPI device is not allowed to send the PECI command to eSPI in Sx states. More specifically, the device can only send PECI requests after Virtual Wire PLT_​RST# de-assertion.

In S0ix, upon receiving a PECI command, the PMC will wake up the CPU from Cx and respond back once the data is available from CP