Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Well

During Reset1

Immediately after Reset1

S0/S3/S4/S5

Deep Sx

EMMC_​DATA[7:0]

Primary

Undriven

Undriven

Undriven

OFF

EMMC_​RCLK

Primary

Undriven

Undriven

Undriven

OFF

EMMC_​CLK

Primary

Undriven

Undriven

Undriven

OFF

EMMC_​CMD

Primary

Undriven

Undriven

Undriven

OFF

EMMC_​RCOMP

Primary

Undriven

Undriven

Undriven

OFF

EMMC_​RESET_​N

Primary

Undriven

Undriven

Undriven

OFF

Notes:
  1. Reset reference for primary well pins is PMC_​RSMRST_​N.