Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents

Exiting Sleep States

Sleep states (S3–S5) are exited based on wake events. The wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state and have to be enabled using a GPIO pin before it can be used.

Upon exit from the PCH-controlled Sleep states, the WAK_​STS bit is set. The possible causes of wake events (and their restrictions) are shown in table below.

Note:(Mobile Only) If the BATLOW# signal is asserted, the PCH does not attempt to wake from an S3–S5 state, nor will it exit from Deep Sx state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the PCH, and the system wakes after BATLOW# is de-asserted.

Cause of Wake Events

Cause How Enabled Wake from Sx Wake from Deep Sx Wake from Sx After Power Loss2 Wake from "Reset" Types3
RTC Alarm Set RTC_​EN bit in PM1_​EN_​STS register. Yes Yes Yes No
Power Button Always enabled as Wake event. Yes Yes Yes Yes
Any GPIOs except DSW GPIOs can be enabled for wake Refer Note 5 Yes No No No
LAN_​WAKE_​N 8 Enabled natively (unless pin is configured to be in GPIO mode) N/A N/A N/A N/A
Intel ® High Definition Audio Event sets PME_​B0_​STS bit; PM_​B0_​EN must be enabled. Can not wake from S5 state if it was entered due to power failure or power button override. Yes No Yes No
Primary PME# PME_​B0_​EN bit in GPE0_​EN[127:96] register. Yes No Yes No
Secondary PME# Set PME_​EN bit in GPE0_​EN[127:96] register. Yes No Yes No
PCI Express* WAKE# pin PCIEXP_​WAKE_​DIS bit. Yes Yes Yes No
SMBALERT# Refer Note 4 Yes No Yes Yes
SMBus Slave Wake Message (01h) Wake/SMI# command always enabled as a Wake event. Note:SMBus Slave Message can wake the system from S3-S5, as well as from S5 due to Power Button Override. Yes No Yes Yes
SMBus Host Notify message received HOST_​NOTIFY_​WKEN bit SMBus Slave Command register. Reported in the SMB_​WAK_​STS bit in the GPE0_​STS register. Yes No Yes Yes
Wake Alarm Device WADT_​EN in GPE0_​EN[127:96] Yes Yes No No
AC_​PRESENT AC_​PRESENT_​WAKE_​EN (Refer Note 6) No Yes No No
USB connection in/after deep-Sx GPE0_​EN.USB_​CON_​DSX_​EN+ Refer Note 7 Yes No No
  1. If BATLOW# signal is low, PCH will not attempt to wake from S3-S5 (nor will it exit Deep Sx), even if valid wake event occurs. This prevents the system from waking when battery power is insufficient to wake the system. However, once BATLOW# goes back high, the system will boot.
  2. This column represents what the PCH would honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss.
  3. Reset Types include: Power Button override, Intel® CSE-initiated power button override, Intel® CSE-initiated host partition reset with power down, Intel® CSE Watchdog Timer, SMBus unconditional power down, processor thermal trip, PCH catastrophic temperature event.
  4. SMBALERT# signal is multiplexed with a GPIO pin that defaults to GPIO mode. Hence, SMBALERT# related wakes are possible only when this GPIO is configured in native mode, which means that BIOS must program this GPIO to operate in native mode before this wake is possible. Because GPIO configuration is in the resume well, wakes remain possible until one of the following occurs: BIOS changes the pin to GPIO mode, a G3 occurs or Deep Sx entry occurs.
  5. There are only 72 bits in the GPE registers to be assigned to GPIOs, though any of the GPIOs can trigger a wake, only those status of GPIO mapped to 1-tier scheme are directly accessible through the GPE status registers. For those GPIO mapped under 2-tier scheme, their status would be reflected under single master status, “GPIO_​TIER2_​SCI_​STS” or GPE0_​STS and further comparison needed to know which 2-tier GPI(s) has triggered the GPIO Tier 2 SCI.
  6. A change in AC_​PRESENT causes an exit from Deep Sx to Sx, but the system will not wake all the way to S0.
  7. Connection of a USB device can cause a wake from normal Sx as well. But that class of wakes is routed through PME_​B0, not through this wake enable. The USB_​CON_​DSX_​EN applies only to connection wakes while in Deep Sx or while in Sx after Deep Sx.

    Sx after Deep Sx reached due to AC_​PRESENT going high while in Deep Sx, if Deep Sx is only enabled while on DC power.

    The following additional conditions are required for this wake to occur:

    1. The bit(s) in PM_​CFG2.USB_​DSX_​PER_​PORT_​EN associated with the port(s) which experienced the connection must be set to ‘1’.
    2. DSX_​CFG.USB_​CON_​DSX_​MODE must be set to ‘1’, routing USB connection to generate a wake rather than be reflected out to a pin.
  8. No Integrated GbE