Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents


From the platform perspective, the FIVRs require an input rail to generate the internal voltage rails. This rail is referred to as VCCIN_​AUX.For the PCH, the input regulator must be able to support at least 1.8 V. During the deep S0ix states, the input rail to the FIVRs can be disabled. This will be done by driving the CORE_​VID values to ‘00. VCCIN_​AUX powergood during initial reset is tied into the PMC_​RSMRST_​N signal, requiring that the FIVR input voltage rail is stable in the same window as the other PMC_​SLP_​SUS_​N rails. Internal FIVRs will generate Vnn, V1P05 rails.

Note:Leakage from VCCIN_​AUX is expected behavior when CORE_​VID[1:0]=00; this leakage voltage may be as high as 1.15 V during Sx and S0ix states