Intel® Pentium® Silver and Intel® Celeron® Processors
Datasheet, Volume 1 of 2
Display Interfaces
| Package Pin | Dir. | eDP | MIPI DSI | DP | HDMI |
|---|---|---|---|---|---|
| DISP_RCOMP | N/A | Common RCOMP for all PHYs | |||
| DDI0_AUXP DDI0_AUXN | I/O | eDP Auxiliary Channel (AUX_CH) | MIPI0 Data 0 | DP0 Auxiliary Channel (AUX_CH) | NC |
| DDI0_TXN0 DDI0_TXP0 | I/O | eDP Main Link, Lane 0 (ML_Lane 0) | MIPI0 Data 1 | DP0 Main Link, Lane 0 (ML_Lane 0) | TMDS0 Data2 |
| DDI0_TXN1 DDI0_TXP1 | O | eDP Main Link, Lane 1 (ML_Lane 1) | MIPI0 Data 2 | DP0 Main Link, Lane 1 (ML_Lane 1) | TMDS0 Data1 |
| DDI0_TXN2 DDI0_TXP2 | O | eDP Main Link, Lane 2 (ML_Lane 2) | MIPI0 Clock | DP0 Main Link, Lane 2 (ML_Lane 2) | TMDS0 Data 0 |
| DDI0_TXN3 DDI0_TXP3 | O | eDP Main Link, Lane 3 (ML_Lane 3) | MIPI0 Data 3 | DP0 Main Link, Lane 3 (ML_Lane 3) | TMDS0 Clock |
| DDI1_AUXN DDI1_AUXP | I/O | NC | MIPI1 Data 0 | DP1 Auxiliary Channel (AUX_CH) | NC |
| DDI1_TXN0 DDI1_TXP0 | I/O | NC | MIPI1 Data 1 | DP1 Main Link, Lane 0 (ML_Lane 0) | TMDS1 Data2 |
| DDI1_TXN1 DDI1_TXP1 | O | NC | MIPI1 Data 2 | DP1 Main Link, Lane 1 (ML_Lane 1) | TMDS1 Data1 |
| DDI1_TXN2 DDI1_TXP2 | O | NC | MIPI1 Clock | DP1 Main Link, Lane 2 (ML_Lane 2) | TMDS1 Data0 |
| DDI1_TXN3 DDI1_TXP3 | O | NC | MIPI1 Data 3 | DP1 Main Link, Lane 3 (ML_Lane 3) | TMDS1 Clock |
| DDI2_AUXN DDI2_AUXP | I/O | NC | NC | DP2 Auxiliary Channel (AUX_CH) | NC |
| DDI2_TXN0 DDI2_TXP0 | I/O | NC | NC | DP2 Main Link, Lane 0 (ML_Lane 0) | TMDS2 Data2 |
| DDI2_TXN1 DDI2_TXP1 | O | NC | NC | DP2 Main Link, Lane 1 (ML_Lane 1) | TMDS2 Data1 |
| DDI2_TXN2 DDI2_TXP2 | O | NC | NC | DP2 Main Link, Lane 2 (ML_Lane 2) | TMDS2 Data0 |
| DDI2_TXN3 DDI2_TXP3 | O | NC | NC | DP2 Main Link, Lane 3 (ML_Lane 3) | TMDS2 Clock |
| Display Signals | Dir. | Description | Usage Model | |||
|---|---|---|---|---|---|---|
| eDP/DP/HDMI Port 0, DP/HDMI Port 1, DP/HDMI Port 2 | DSI Dual Link Port 0+1, DP/HDMI Port 2 | DSI Port 0, DP/HDMI port 1, DP/HDMI Port 2(Note1) | DSI Port 0, DP/HDMI Port 2 (Note2) | |||
| DDI0_HPD | I/O | DDI0 Hot Plug Detection | DDI0 eDP HPD |
|
| |
| DDI1_HPD | I/O | DDI1 Hot Plug Detection | DP/HDMI HPD | DDI1 DP/HDMI HPD | ||
| eDP_VDDEN | I/O | Panel main power enable | VDD enable for eDP | MIPI DSI power enable AVDD | MIPI DSIPower Enable AVDD | MIPI DSI Power Enable AVDD |
| DDI2_HPD | I | Dedicated DDI2 Hot Plug Detection | DDI2 DP/HDMI HPD | DDI2 DP/HDMI HPD | DDI2 DP/HDMI HPD | DDI2 DP/HDMI HPD |
| eDP_BKLTEN | O | Panel backlight enable | eDP Backlight Enable | MIPI DSI Backlight Enable | MIPI DSI Backlight Enable | MIPI DSI Backlight Enable |
| eDP_BKLTCTL | O | Panel backlight control | eDP Backlight Control | MIPI DSI Backlight Control | MIPI DSI Backlight Control | MIPI DSI Backlight Control |
| DDI0_DDC_SCL | I/O | Panel reset or DDC clock for HDMI 0 or DSI panel secondary power (AVEE) | Control Clock 0 | DSI power AVEE | MIPI0 Reset | DSI power AVEE |
| DDI0_DDC_SDA | I/O | DDC data for HDMI 0 or DSI panel secondary power (AVDD) | Control Data 0 | DSI power AVDD | DSI power AVEE | DSI power AVEE |
| DDI1_DDC_SCL | I/O | Panel reset or DDC clock for HDMI 1 | Control Clock 1 | Dual Link Mode Reset | Control Clock 1 | MIPI0 Reset |
| DDI1_DDC_SDA | I/O | DDC data for HDMI 1 | Control Data 1 | Control Data 1 | ||
| DDI2_DDC_SCL | I/O | Dedicated DDI2 DDC Clock for HDMI or DP++ | Control Clock 2 | Control Clock 2 | Control Clock 2 | Control Clock 2 |
| DDI2_DDC_SDA | I/O | Dedicated DDI2 DDC Data for HDMI and DP++ | Control Data 2 | Control Data 2 | Control Data 2 | DDI2 DDC Data |
| MDSI_DE_TE_1 | I/O | Tearing Effect from MIPI Panel 0 | Dual link MIPI TE | MIPI0 TE | MIPI0 TE | |
| MDSI_DE_TE_2 | I/O | Tearing Effect from MIPI Panel 1 | Dual link MIPI TE | |||