Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents

FSPI Support for TPM

The PCH’s FSPI flash controller supports a discrete TPM on the platform via its dedicated FSPI_​CS2_​N signal. The platform must have no more than One TPM.

SPI controller supports accesses to SPI TPM at 20 MHz, 33 MHz and 60 MHz depending on the PCH soft strap. 20 MHz is the reset default, a valid PCH soft strap setting overrides the requirement for the 20 MHz. SPI TPM device must support a clock of 20 MHz. It may, but is not required to support a frequency greater than 20 MHz. The SPI controller does have an integrated interrupt signal for the TPM.