Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

System Memory Timing Support

The IMC supports the following DDR Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

  • tCL = CAS Latency
  • tRCD = Activate Command to READ or WRITE Command delay
  • tRP = PRECHARGE Command Period
  • tRPb = per-bank PRECHARGE time
  • tRPab = all-bank PRECHARGE time
  • CWL = CAS Write Latency
  • Command Signal modes:
    • 2N indicates a new DDR4 command may be issued every 2 clocks.
    • 1N indicates a new DDR4/LPDDR4x command may be issued every clock.

DDR4 System Memory Timing Support

DRAM Device

Transfer Rate (MT/s)

tCL (tCK)

tRCD (ns)

tRP (ns)

CWL (tCK)

DPC

CMD Mode

DDR4

2933

22

13.75

13.75

9-12, 14,16,18,20

1

2N

LPDDR4x System Memory Timing Support 

DRAM Device

Mode

Transfer Rate (MT/s)

tCL (tCK)

tRCD (ns)

tRPpb (ns)

tRPab (ns)

WL (tCK) Set B

LPDDR4x

X32

2933

36

18

18

21

30