Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents

Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers

The PCH implements three independent UART interfaces, UART0, UART1 and UART2. Each UART interface is a 4-wire interface supporting up to 6.25 Mbit/s.

The interfaces can be used in the low-speed, full-speed, and high-speed modes. The UART communicates with serial data ports that conform to the RS-232 interface protocol.

UART2 only implements the UART Host controller and does not incorporate a DMA controller which is implemented for UART0 and UART1. Therefore, UART2 is restricted to operate in PIO mode only

The UART interfaces support the following features:

  • Up to 6.25 Mbits/s Auto Flow Control mode as specified in the 16750 standard
  • Transmitter Holding Register Empty (THRE) interrupt mode
  • 64-byte TX and 64-byte RX host controller FIFOs
  • DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)
  • Functionality based on the 16550 industry standards
  • Programmable character properties, such as number of data bits per character (5-8), optional parity bit (with odd or even select) and number of stop bits (1, 1.5, or 2)
  • Line break generation and detection
  • DMA signaling with two programmable modes
  • Prioritized interrupt identification
  • Programmable FIFO enable/disable
  • Programmable serial data baud rate
  • Modem and status lines are independently controlled
  • Programmable BAUD RATE supported (baud rate = (serial clock frequency)/(16xdivisor))

  1. SIR mode is not supported.
  2. External read enable signal for RAM wake up when using external RAMs is not supported.





Direct Memory Access


Universal Asynchronous Receiver/Transmitter