Intel® Pentium® Silver and Intel® Celeron® Processors
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
633935 | 12/27/2022 | Public |
Legal Disclaimer
Revision History
Introduction
Technologies
Power Management
Thermal Management
Memory
Graphics
Display
Imaging
Pin Strap
General Purpose Input and Output (GPIO)
PCH Electrical Specification
CPU Electrical Specifications
Global Device IDs
CPU And Device IDs
Audio, Voice, and Speech
Connectivity Integrated (CNVi)
PCI Express* (PCIe*)
Universal Serial Bus (USB)
Serial ATA (SATA)
Flexible I/O
Storage
Serial Peripheral Interface (SPI)
Intel® Serial I/O Generic SPI (GSPI) Controllers
Enhanced Serial Peripheral Interface (eSPI)
Real Time Clock (RTC)
8254 Timers
High Precision Event Timer (HPET)
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers
Host System Management Bus (SMBus) Controller
System Management Interface and SMLink
System Management
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Testability
SoC Pin Location
Security Technologies
Branch Monitoring Counters
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation via SD3_RCOMP
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO (TIME_SYNC)
GPIO Blink (BK) and Serial Blink (SBK)
Interrupt / IRQ via GPIO Requirement
Native Function and TERM Bit Setting
Virtual GPIO (vGPIO)
DC Specifications
Display Port* Specification
HDMI* Specifications
embedded Display Port* Specifications
16550 8-bit Addressing - Debug Driver Compatibility
SVID AC Specifications
MIPI* DSI Specification
Memory Specifications
MIPI* CSI Specifications
CMOS DC Specifications
GTL and Open Drain DC Specification
PECI DC Characteristics
Features Supported
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single- Root I/O Virtualization (SR- IOV)
SERR# Generation
Hot-Plug
PCI Express* Lane Polarity Inversion
PCI Express* Controller Lane Reversal
Precision Time Measurement (PTM)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
The PCH implements three independent UART interfaces, UART0, UART1 and UART2. Each UART interface is a 4-wire interface supporting up to 6.25 Mbit/s.
The interfaces can be used in the low-speed, full-speed, and high-speed modes. The UART communicates with serial data ports that conform to the RS-232 interface protocol.
UART2 only implements the UART Host controller and does not incorporate a DMA controller which is implemented for UART0 and UART1. Therefore, UART2 is restricted to operate in PIO mode only
The UART interfaces support the following features:
- Up to 6.25 Mbits/s Auto Flow Control mode as specified in the 16750 standard
- Transmitter Holding Register Empty (THRE) interrupt mode
- 64-byte TX and 64-byte RX host controller FIFOs
- DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)
- Functionality based on the 16550 industry standards
- Programmable character properties, such as number of data bits per character (5-8), optional parity bit (with odd or even select) and number of stop bits (1, 1.5, or 2)
- Line break generation and detection
- DMA signaling with two programmable modes
- Prioritized interrupt identification
- Programmable FIFO enable/disable
- Programmable serial data baud rate
- Modem and status lines are independently controlled
- Programmable BAUD RATE supported (baud rate = (serial clock frequency)/(16xdivisor))
- SIR mode is not supported.
- External read enable signal for RAM wake up when using external RAMs is not supported.
Acronyms | Description |
---|---|
DMA | Direct Memory Access |
UART | Universal Asynchronous Receiver/Transmitter |