Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
633935 12/27/2022 Public
Document Table of Contents
DSP

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately after Reset1

S3/S4/S5

Deep Sx

UART[2:0]_​RXD

Primary

Undriven

Undriven

Undriven

OFF

UART[2:0]_​TXD

Primary

Undriven

Undriven

Undriven

OFF

UART[2:0]_​RTS_​N

Primary

Undriven

Undriven

Undriven

OFF

UART[2:0]_​CTS_​N

Primary

Undriven

Undriven

Undriven

OFF

Notes:
  1. Reset reference for primary well pins is PMC_​RSMRST_​N.