General DC Characteristics

Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
633935	12/27/2022		Public

Single-Ended Signal DC Characteristics as Inputs or Outputs

Type	Symbol	Parameter	Minimum	Maximum	Unit	Condition	Notes
Notes: For GPIO supported voltages, refer to General Purpose Input and Output (GPIO). Maximum overshoot voltage is 2.19 V Min undershoot voltage is -0.28
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.
Associated Signals¹: GP_G00/SD_SDIO_CMD, GP_G01/SD_SDIO_D0, GP_G02/SD_SDIO_D1, GP_G03/SD_SDIO_D2, GP_G04/SD_SDIO_D3, GP_G05/SD_SDIO_CD_N, GP_G06/SD_SDIO_CLK, GP_G07/SD_SDIO_WP
3.3 V Operation
Input	VIH	Input High Voltage Threshold	0.75 x VCC		V
	VIL	Input Low Voltage Threshold		0.25 x VCC	V
	IIL	Input Leakage Current	-14	14	µA
	CIN	Input Pin Capacitance		14	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.3 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.7 * VCC
1.8 V Operation
Input	VIH	Input High Voltage Threshold	0.75 x VCC		V
	VIL	Input Low Voltage Threshold		0.25 x VCC	V
	IIL	Input Leakage Current	-14	14	µA
	CIN	Input Pin Capacitance		14	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.3 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.7 * VCC
Notes: For GPIO supported voltages, refer to General Purpose Input and Output (GPIO) If GP_G[00:07] are used for SD functionality, pins are dynamically configured based on SD card capability otherwise if used as GPIO it can be configured to 3.3V or 1.8V.
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.
Associated Signals¹: GP_DSW09/PMC_SLP_WLAN_N, GP_DSW08/PMC_SUSCLK, GP_DSW07, GP_DSW06/PMC_SLP_A_N, GP_DSW05/PMC_SLP_S4_N, GP_DSW04/PMC_SLP_S3_N, GP_DSW03/PMC_PWRBTN_N, GP_DSW02/LAN_WAKE_N, GP_DSW10/PMC_SLP_S5_N, GP_DSW01/PMC_ACPRESENT, GP_DSW00/PMC_BATLOW_N, PMC_SLP_SUS_N, PMC_WAKE_N, PMC_DRAM_RESET_N
3.3 V Operation
Input	V_IH	Input High Voltage Threshold	0.75 x VCC		V
	V_IL	Input Low Voltage Threshold		0.25 x VCC	V
	I_IL	Input Leakage Current	-10	10	µA
	C_IN	Input Pin Capacitance		14	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA
	R_pu	WPU 5K/20K Resistance	1K-50% 5K-70% 20K-35%	1K+100% 5K+70% 20K+35%	Ohm	0.7 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-35%	5K+70% 20K+35%	Ohm	0.3 * VCC
Note:For GPIO supported voltages, refer to General Purpose Input and Output (GPIO).
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.
Associated Signals¹: GP_B09/PCIE_CLKREQ4_N, GP_B08/PCIE_CLKREQ3_N, GP_B07/PCIE_CLKREQ2_N, GP_B06/PCIE_CLKREQ1_N, GP_B05/PCIE_CLKREQ0_N, GP_B04/CPU_GP_3, GP_B03/CPU_GP_2, GP_B23/DDI2_HPD/TIME_SYNC_0/GSPI1_CS1_N, GP_B22/GSPI1_MOSI, GP_B21/GSPI1_MISO/NFC_CLKREQ, GP_B20/GSPI1_CLK/NFC_CLK, GP_B02/PMC_VRALERT_N, GP_B19/GSPI1_CS0_N, GP_B18/GSPI0_MOSI/UART2A_TXD, GP_B17/GSPI0_MISO/UART2A_RXD, GP_B16/GSPI0_CLK, GP_B15/GSPI0_CS0_N, GP_B14/SPKR_GSPI0_CS1_N, GP_B13/PMC_PLTRST_N, GP_B12/PMC_SLP_S0_N, GP_B11/PMCALERT_N, GP_B10/PCIE_CLKREQ5_N, GP_B01/PMC_CORE_VID1, GP_B00/PMC_CORE_VID0, GP_H09/I2C4_SCL, GP_H08/I2C4_SDA, GP_H07/I2C3_SCL, GP_H06/I2C3_SDA, GP_H05/I2C2_SCL, GP_H04/I2C2_SDA, GP_H03/SX_EXIT_HOLDOFF_N, , GP_H02/MODEM_CLKREQ, GP_H19, GP_H18, GP_H17, GP_H16, GP_H15/AVS_I2S1_SCLK , GP_H14/AVS_I2S2_RXD, GP_H13/AVS_I2S2_TXD/MODEM_CLKREQ, GP_H12/AVS_I2S2_SFRM/CNV_RF_RESET_N, GP_H11/AVS_I2S2_SCLK, GP_H10/CPU_C10_GATE_N, GP_H01/SD_SDIO_PWR_EN_N/CNV_RF_RESET_N, GP_H00, GP_D09/GSPI2_CLK/UART0A_TXD, GP_D08/GSPI2_SPI2_CS0_N/UART0A_RXD, GP_D07, GP_D06, GP_D05, GP_D04, GP_D03/BK_3/SBK_3, GP_D23/I2C5_SCL, GP_D22/I2C5_SDA, GP_D21/CNV_PA_BLANKING, GP_D20/CNV_MFUART2_TXD, GP_D02/BK_2/SBK_2, GP_D19/CNV_MFUART2_RXD, GP_D18/AVS_I2S_MCLK, GP_D17, GP_D16, GP_D15/CNV_WCEN, GP_D14/GSPI2_CS1_N, GP_D13/I2C4B_SCL, GP_D12/I2C4B_SDA, GP_D11/GSPI2_MOSI/UART0A_CTS_N, GP_D10/GSPI2_MISO/UART0A_RTS_N, GP_D01/BK_1/SBK_1, GP_D00/BK_0/SBK_0, GP_C09/UART0_TXD, GP_C08/UART0_RXD, GP_C07/PMC_SUSACK_N, GP_C06/PMC_SUSWARN_N/PMC_SUSPWRDNACK, GP_C05, GP_C04, GP_C03,GP_C23/UART2_CTS_N/CNV_MFUART0_CTS_N, GP_C22/UART2_RTS_N/CNV_MFUART0_RTS_N, GP_C21/UART2_TXD/CNV_MFUART0_TXD, GP_C20/UART2_RXD/CNV_MFUART0_RXD, GP_C02, GP_C19/I2C1_SCL, GP_C18/I2C1_SDA, GP_C17/I2C0_SCL, GP_C16/I2C0_SDA, GP_C15/UART1_CTS_N, GP_C14/UART1_RTS_N, GP_C13/UART1_TXD, GP_C12/UART1_RXD, GP_C11/UART0_CTS_N, GP_C10/UART0_RTS_N, GP_C01, GP_C00
3.3 V Operation
Input	V_IH	Input High Voltage Threshold	0.75 x VCC		V
	V_IL	Input Low Voltage Threshold		0.25 x VCC	V
	I_IL	Input Leakage Current	-12	12	µA
	C_IN	Input Pin Capacitance		10	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	1K-50% 5K-70% 20K-35%	1K+100% 5K+70% 20K+35%	Ohm	0.7 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-35%	5K+70% 20K+35%	Ohm	0.3 * VCC
1.8 V Operation
Input	V_IH	Input High Voltage Threshold	0.75 x VCC		V
	V_IL	Input Low Voltage Threshold		0.25 x VCC	V
	I_IL	Input Leakage Current	-12	12	µA
	C_IN	Input Pin Capacitance		10	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	1K-50% 5K-70% 20K-35%	1K+100% 5K+70% 20K+35%	Ohm	0.7 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-35%	5K+70% 20K+35%	Ohm	0.3 * VCC
Notes: For GPIO supported voltages, refer to General Purpose Input and Output (GPIO) When eSPI is enabled, SX_EXIT_HOLDOFF_N functionality is not available, and assertion of the signal will not impact Sx exit flows.
Note:For GPIO pads (GP) listed in the Associated Signals below, all functions that are multiplexed on GPIO pads will have the same DC characteristics as the GPIO pads. Refer to the General Purpose Input and Output (GPIO) for the multiplexed functions on a specific GPIO pad.
Associated Signals¹: GP_A09/SMB_ALERT_N, GP_A08/SMB_DATA, GP_A07/SMB_CLK, GP_A06/ESPI_RESET_N, GP_A05/ESPI_CLK, GP_A04/ESPI_CS_N, GP_A03/ESPI_IO_3, GP_A02/ESPI_IO_2, GP_A19/PCHHOT_N, GP_A18/USB_OC0_N, GP_A17/DDI0_HPD, GP_A16/DDI1_HPD/TIME_SYNC_1, GP_A15, GP_A14/USB_OC3_N, GP_A13/USB_OC2_N, GP_A12/USB_OC1_N, GP_A11/CPU_GP_1, GP_A10/CPU_GP_0, GP_A01/ESPI_IO_1, GP_A00/ESPI_IO_0, GP_E09/SML_CLK0/SATA_1_GP, GP_E08/SATA_0_GP, GP_E07/SATA_1_DEVSLP, GP_E06/IMGCLKOUT_3, GP_E05/SATA_LED_N, GP_E04/IMGCLKOUT_2, GP_E03/SATA_0_DEVSLP, GP_E23/CNV_RGI_RSP, GP_E22/CNV_RGI_DT, GP_E21/CNV_BRI_RSP, GP_E20/CNV_BRI_DT, GP_E02/IMGCLKOUT_1, GP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN, GP_E18/DDI2_DDC_SDA/BSSB_LS2_TX, GP_E17/DDI2_DDC_SCL/BSSB_LS2_RX, GP_E16/DDI1_DDC_SDA/BSSB_LS1_TX, GP_E15/DDI1_DDC_SCL/BSSB_LS1_RX, GP_E14/DDI0_DDC_SDA/BSSB_LS0_TX, GP_E13/DDI0_DDC_SCL/BSSB_LS0_RX, GP_E12/IMGCLKOUT_4/BSSB_LS3_TX, GP_E11/BSSB_LS3_RX, GP_E10/SML_DATA0, GP_E01, GP_E00/IMGCLKOUT_0
3.3 V Operation
Input	V_IH	Input High Voltage Threshold	0.75 x VCC		V
	V_IL	Input Low Voltage Threshold		0.25 x VCC	V
	I_IL	Input Leakage Current	-14	14	µA
	C_IN	Input Pin Capacitance		14	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.7 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.3 * VCC
1.8 V Operation
Input	V_IH	Input High Voltage Threshold	0.75 x VCC		V
	V_IL	Input Low Voltage Threshold		0.25 x VCC	V
	I_IL	Input Leakage Current	-14	14	µA
	C_IN	Input Pin Capacitance		14	pF
Output	V_OH	Output High Voltage Threshold	VCC - 0.45	VCC	V	IOH=3 mA	Only for 50 ohm mode
	V_OL	Output Low Voltage Threshold		0.45	V	IOL=-3 mA	Only for 50 ohm mode
	R_pu	WPU 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.3 * VCC
	R_pd	WPD 5K/20K Resistance	5K-70% 20K-25%	5K+70% 20K+35%	Ohm	0.7 * VCC
Notes: For GPIO supported voltages, refer to General Purpose Input and Output (GPIO) If GP_A[00:06] is used for eSPI it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V If GP_E[11:18] is used for BSSB it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V If GP_E[20:23] is used for CNVi it can be configured to 1.8V only otherwise if used as GPIO it can be configured to 3.3V or 1.8V

Single-Ended Signal DC Characteristics as Inputs or Outputs

Type	Symbol	Parameter	Minimum	Maximum	Unit	Notes
Associated Signals: INTRUDER_N, PMC_RSMRST_N, PMC_PCH_PWROK, PMC_DSW_PWROK, SRTCRST_N
Input	VIH	Input High Voltage Threshold	0.65 x VCCRTC	VCCRTC+0.5	V	4, 6
Input	VIL	Input Low Voltage Threshold	-0.5	0.3 x VCCRTC	V	6
Associated Signals: RTCRST_N
Input	VIH	Input High Voltage Threshold	0.75 x VCCRTC	V VCCRTC+0.5	V	4, 5, 6
Input	VIL	Input Low Voltage Threshold	-0.5	0.4 x VCCRTC	V	6
Associated Signals: RTCX1
Input	VIH	Input High Voltage Threshold	0.8	1.2	V
Input	VIL	Input Low Voltage Threshold	-0.5	0.1	V
Notes: The V_OH specification does not apply to open-collector or open-drain drivers. Signals of this type must have an external Pull-up resistor, and that is what determines the high-output voltage level. Input characteristics apply when a signal is configured as Input or to signals that are only Inputs. Output characteristics apply when a signal is configured as an Output or to signals that are only Outputs. Vpk-pk minimum for XTAL24 = 500 mV VCCRTC is the voltage applied to the VCCRTC well of the PCH. When the system is in G3 state, it is generally supplied by the coin cell battery. In S5 or greater state, it is supplied by VCCSUS3_3 V_IH min should not be used as the reference point for T200 timing. Refer T200 specification for the measurement point detail These buffers have input hysteresis. V_IH levels are for rising edge transitions and V_IL levels are for falling edge transitions.

Signal Characteristics

Symbol	Parameter	Minimum	Maximum	Unit	Conditions	Notes
Associated Signals: PCIe*						9, 10
Gen 1
VTX-DIFF P-P	Differential Peak to Peak Output Voltage	0.8	1.2	V		1
VTX-DIFF P-P - Low	Low power differential Peak to Peak Output Voltage	0.4	1.2	V
VTX_CM-ACp	TX AC Common Mode Output Voltage (2.5 GT/s)	—	20	mV
ZTX-DIFF-DC	DC Differential TX Impedance	80	120	Ohm
VRX-DIFF p-p	Differential Input Peak to Peak Voltage	0.12	1.2	V		1
VRX_CM-ACp	AC peak Common Mode Input Voltage	—	150	mV
Gen 2
VTX-DIFF P-P	Differential Peak to Peak Output Voltage	0.8	1.2	V
VTX-DIFF P-P - Low	Low power differential Peak to Peak Output Voltage	0.4	1.2	V
ZTX-DIFF-DC	DC Differential TX Impedance	80	120	Ohm
VRX-DIFF p-p	Differential Input Peak to Peak Voltage	0.12	1.2	V
VRX_CM-ACp	AC peak Common Mode Input Voltage	—	150	mV
Gen 3
VTX-DIFF P-P	Differential Peak to Peak Output Voltage	0.8	1.3	V
VTX-DIFF P-P - Low	Low power differential Peak to Peak Output Voltage	0.4	1.2	V
ZTX-DIFF-DC	DC Differential TX Impedance	80	120	Ohm
VRX-DIFF p-p	Differential Input Peak to Peak Voltage	Refer to Stressed Voltage Eye Parameters Table in PCIe* Gen 3 industry specifications.
VRX_CM-ACp	AC peak Common Mode Input Voltage	—	150	mV
Associated Signals: SATA
VIMIN-Gen1i	Minimum Input Voltage - 1.5 Gb/s internal SATA	325	—	mVdiff p-p		2
VIMAX-Gen1i	Maximum Input Voltage - 1.5 Gb/s internal SATA	—	600	mVdiff p-p		2
VIMIN-Gen1m	Minimum Input Voltage - 1.5 Gb/s eSATA	240	—	mVdiff p-p		2
VIMAX-Gen1m	Maximum Input Voltage - 1.5 Gb/s eSATA	—	600	mVdiff p-p		2
VIMIN-Gen2i	Minimum Input Voltage - 3.0 Gb/s internal SATA	275	—	mVdiff p-p		2
VIMAX-Gen2i	Maximum Input Voltage - 3.0 Gb/s internal SATA	—	750	mVdiff p-p		2
VIMIN-Gen2m	Minimum Input Voltage - 3.0 Gb/s eSATA	240	—	mVdiff p-p		2
VIMAX-Gen2m	Maximum Input Voltage - 3.0 Gb/s eSATA	—	750	mVdiff p-p		2
VIMIN-Gen3i	Minimum Input Voltage - 6.0 Gb/s internal SATA	240	—	mVdiff p-p		2
VIMAX-Gen3i	Maximum Input Voltage - 6.0 Gb/s internal SATA	—	1000	mVdiff p-p		2
VOMIN-Gen1i,m	Minimum Output Voltage 1.5 Gb/s internal and eSATA	400	—	mVdiff p-p		3
VOMIN-Gen2i,m	Minimum Output Voltage 3.0 Gb/s internal and eSATA	400	—	mVdiff p-p		3
VOMIN-Gen3i	Minimum Output Voltage 6.0 Gb/s internal SATA	200	—	mVdiff p-p		3
VOMAX-Gen3i	Maximum Output Voltage 6.0 Gb/s internal SATA	—	900	mVdiff p-p		3
Associated Signals: USB 2.0
VDI	Differential Input Sensitivity	0.2	—	V		4, 6
VCM	Differential Common Mode Range	0.8	2.5	V		5, 6
VSE	Single-Ended Receiver Threshold	0.8	2	V		6
VCRS	Output Signal Crossover Voltage	1.3	2	V		6
VOL	Output Low Voltage	—	0.4	V	I_OL=5 mA	6
VOH	Output High Voltage	3.3V – 0.5	—	V	I_OH=-2 mA	6
VHSSQ	HS Squelch Detection Threshold	100	150	mV		7
VHSDSC	HS Disconnect Detection Threshold	525	625	mV		7
VHSCM	HS Data Signaling Common Mode Voltage Range	-50	500	mV		7
VHSOI	HS Idle Level	-10	10	mV		7
VHSOH	HS Data Signaling High	360	440	mV		7
VHSOL	HS Data Signaling Low	-10	10	mV		7
VCHIRPJ	Chirp J Level	700	1100	mV		7
VCHIRPK	Chirp K Level	-900	-500	mV		7
New: VDI VCM, VSE, VCRS, VOL, VOH are USB 2.0 FS/LS electrical characteristic.
Associated Signals: USB 3.2
VTX-DIFF-PP	Differential Peak to Peak Output Voltage	0.8	1.2	V
VTX-DIFF P-P - Low	Low power differential Peak to Peak Output Voltage	0.4	1.2	V		8
VTX_CM-Acp-p	TX AC Common Mode Output Voltage (5GT/s)	—	100	mV
ZTX-DIFF-DC	DC Differential TX Impedance	72	120	Ohm
VRX-DIFF p-p	Differential Input Peak to Peak Voltage	0.1	1.2	V
VRX_CM-ACp	AC peak Common Mode Input Voltage	—	150	mV
Notes: PCI Express* mVdiff p-p = 2\|PCIE[x]_TXP – PCIE[x]_TXN\|; PCI Express mVdiff p-p = 2\|CIE[x]_RXP – PCIE[x]_RXN\| SATA Vdiff, RX (V_IMAX/V_IMIN) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2\|SATA[x]RXP – SATA[x]RXN\|. SATA Vdiff, tx (V_OMIN/V_OMAX) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = 2\|SATA[x]TXP – SATA[x]TXN\| V_DI = \| USBPx[P] – USBPx[N] \| Includes VDI range. Applies to Low-Speed/Full-Speed USB. Applies to High-Speed USB 2.0. USB 3.2 mVdiff p-p = 2\|USB3Rp[x] – USB3Rn[x]\|; USB 3.1 mVdiff p-p = 2\|USB3Tp[x] – USB3Tn[x]\| For PCIe, GEN1, GEN and GEN3 correspond to the PCIe base specification revision 1, 2 and 3. PCIe* specifications are also applicable to the LAN port. Measurement taken from single-ended waveform on a component test board. Measurement taken from differential waveform on a component test board. VCross is defined as the voltage where Clock = Clock#. Only applies to the differential rising edge (that is, Clock rising and Clock# falling). The maximum voltage including overshoot. The minimum voltage including undershoot. The total variation of all VCross measurements in any particular system. Note that this is a subset of VCross MIN/MAX (VCross absolute) allowed. The intent is to limit VCross induced modulation by setting VCross_Delta to be smaller than VCross absolute.