Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID 633935
Date 12/27/2022
Document Table of Contents

FSPI for Flash

The Serial Peripheral Interface (FSPI) supports two SPI flash devices via two chip select signals (FSPI_​CS0_​N and FSPI_​CS1_​N). The maximum size of flash supported is determined by the SFDP-discovered addressing capability of each device. Each component can be up to 16 MB (32 MB total addressable) using 3-byte addressing. Each component can be up to 64 MB (128 MB total addressable) using 4-byte addressing.

PCH drives the interface clock at either 20 MHz, 33 MHz,50 MHz or 60 MHz(1 Load) and will function with flash devices that support at least one of these frequencies.

A SPI flash device supporting SFDP (Serial Flash Discovery Parameter) is required for all PCH designs. A SPI flash device with a valid descriptor MUST be attached directly to the PCH.

The PCH supports fast read which consist of:

  1. Dual Output Fast Read (Single Input Dual Output)
  2. Dual I/O Fast Read (Dual Input Dual Output)
  3. Quad Output Fast Read (Single Input Quad Output)
  4. Quad I/O Fast Read (Quad Input Quad Output)

Operational Modes

The SPI Controller has one operational mode:

Descriptor Mode: This mode is required to enable the following SoC features:

  • Converged Security Engine.
  • Secure Boot.
  • PCI Express* root port configuration.
  • Supports for two SPI components using two separate chip select pins.
  • Hardware enforced security restricting master accesses to different regions.
  • Soft Strap region providing the ability to use Flash NVM to remove the need for pull-up/pull-down resistors for strapping processor features.
  • Support for the SPI Fast Read instruction and frequencies greater than 20 MHz.
  • Support for Single Input, Dual Output Fast reads.
  • Use of standardized Flash instruction set.

SPI Flash Regions

In Descriptor Mode, the Flash is divided into separate regions.

SPI Flash Regions




Flash Descriptor




Converged Security Engine




Platform Data



Only two masters can access the regions: Host processor running BIOS code and the Intel® CSE (Converged Security Engine).

The Flash Descriptor and CSE region are the only required regions. The Flash Descriptor has to be in region 0 and region 0 must be located in the first sector of Device 0 (Offset 0). All other regions can be organized in any order.

Regions can extend across multiple components, but must be contiguous.

Flash Region Sizes

SPI flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4-KB or larger block. The amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the CSE and BIOS regions. The CSE region contains firmware to support CSE capabilities.

Region Size Versus Erase Granularity of Flash Components 


Size with 4-KB


Size with 8-KB Blocks

Size with 64-KB Blocks


4 KB

8 KB

64 KB


Varies by Platform

Varies by Platform

Varies by Platform

Intel® CSE

Varies by Platform

Varies by Platform

Varies by Platform


The bottom sector of the flash component 0 contains the Flash Descriptor. The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the first block. The flash descriptor requires its own block at the bottom of memory (00h). The information stored in the Flash Descriptor can only be written during the manufacturing process as its read/write permissions must be set to read only when the computer leaves the manufacturing floor.

The Flash Descriptor is made up of eleven sections as shown below.

Flash Descriptor Regions

  • OEM Section is 256 bytes reserved at the top of the Flash Descriptor for use by OEM.
  • Descriptor Upper MAP determines the length and base address of the Management Engine VSCC Table.
  • VSCC Table holds the JEDEC ID and the VSCC information of the entire SPI Flash supported by the NVM image.
  • Reserved region between the top of the processor strap section and the bottom of the OEM Section is reserved for future chipset usages.
  • PCH Soft Straps section contains processor and PCH configurable parameters.
  • Master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor ID.
  • Region section points to the three other regions as well as the size of each region.
  • Component section has information about the SPI flash in the system including: the number of components, density of each, invalid instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions.
  • Descriptor Map has pointers to the other five descriptor sections as well as the size of each.
  • Signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 10h) must be 0FF0A55Ah in order to be in Descriptor mode.

Descriptor Master Region

The master region defines read and write access setting for each region of the SPI device. The master region recognizes two masters: BIOS and CSE. Each master is only allowed to do direct reads of its primary regions.

Region Access Control

Master Read/Write Access


Processor and BIOS

Intel® CSE







Flash Descriptor CPU Complex Soft Strap Section

Region Name

Starting Address



Component FCBA


Regions FRBA


Masters FMBA






PMC Straps


CPU Straps


Intel® CSE Straps


Register Init FIBA


Flash Access

There are two types of accesses:

  • Direct Access and
  • Program Register Accesses.

Direct Access

  • Masters are allowed to do direct read only of their primary region
  • The BIOS or CSE virtual read address is converted into the SPI Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers

Direct Access Security

  • Requester ID of the device must match that of the primary Requester ID in the Master Section
  • Calculated Flash Linear Address must fall between primary region base/limit. If it does not, the cycle will not be run on the SPI bus, a completion with not data will be synthesized and returned with an Unsupported Request completion status and the AEL (Access Error Log) register error bit will be set
  • Direct Write is not allowed with the exception of SPI TPM accesses
  • Direct Read Cache contents are reset to 0's on a read from a different master

Program Register Access

  • Program Register Accesses are not allowed to cross a 4-KB boundary and can not issue a command that might extend across two components
  • Software programs the FLA corresponding to the region desired
    • Software must read devices Primary Region Base/Limit address to create FLA.

Register Access Security

  • Only primary region masters can access the registers. If master ID is not valid, the cycle will not be run on the SPI bus, a a completion with no data will be synthesized and returned with an Unsupported Request completion status and the AEL (Access Error Log) register error bit will be set.