Intel® Pentium® Silver and Intel® Celeron® Processors
Datasheet, Volume 1 of 2
ID | Date | Version | Classification |
---|---|---|---|
633935 | 12/27/2022 | Public |
Signal Description
MIPI CSI Port A and Port C can be configured as x4.
Camera Signals | Description |
---|---|
MCSI_A_CKP | Differential clock (Port A) |
MCSI_A_CKN | Differential clock (Port A) |
MCSI_A_D0P | Lane 0 Differential data (Port A) |
MCSI_A_D0N | Lane 0 Differential data (Port A) |
MCSI_A_D1P | Lane 1 Differential data (Port A) |
MCSI_A_D1N | Lane 1 Differential data (Port A) |
MCSI_B_D1P_A_D2P | Differential data (Lane 1 Port B/Lane 2 Port A) |
MCSI_B_D1N_A_D2N | Differential data (Lane 1 Port B/Lane 2 Port A) |
MCSI_B_D0P_A_D3P | Differential data (Lane 0 Port B/Lane 3 Port A) |
MCSI_B_D0N_A_D3N | Differential data (Lane 0 Port B/Lane 3 Port A) |
MCSI_B_CKP | Differential clock (Port B) |
MCSI_B_CKN | Differential clock (Port B) |
MCSI_C_CKP | Differential clock (Port C) |
MCSI_C_CKN | Differential clock (Port C) |
MCSI_C_D0P | Lane 0 Differential data (Port C) |
MCSI_C_D0N | Lane 0 Differential data (Port C) |
MCSI_C_D1P | Lane 1 Differential data (Port C) |
MCSI_C_D1N | Lane 1 Differential data (Port C) |
MCSI_D_D1P_C_D2P | Differential data (Lane 1 Port D/Lane 2 Port C) |
MCSI_D_D1N_C_D2N | Differential data (Lane 1 Port D/Lane 2 Port C) |
MCSI_D_D0P_C_D3P | Differential data (Lane 0 Port D/Lane 3 Port C) |
MCSI_D_D0N_C_D3N | Differential data (Lane 0 Port D/Lane 3 Port C) |
MCSI_D_CKP | Differential clock (Port D) |
MCSI_D_CKN | Differential clock (Port D) |
MCSI_RCOMP | Compensation Resistor |