Panel Power Sequencing and Backlight Control

Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
633935	12/27/2022		Public

The PCH continues to integrate Panel power sequencing and Backlight control signals for eDP* interfaces on the processor.

This section provides details for the power sequence timing relationship of the panel power, the backlight enable, and the eDP* data timing delivery. To meet the panel power timing specification requirements two signals, eDP_VDDEN and eDP_BKLTEN, are provided to control the timing sequencing function of the panel and the backlight power supplies.

A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The panel VDD power, the backlight on/off state, and the eDP* data lines are all managed by an internal power sequencer.

Panel Power Sequencing

Notes:

Support for programming

g parameters TX and T1 through T5 using software is provided.

DisplayPort* Hot-Plug Detect Interface

Signal Group: DDI[0:2]_HPD
Symbol	Parameter	Minimum	Maximum	Unit	Figures	Notes
Tir	Input Time Rise	50	500	ps
Tif	Input Time Fall	50	500	ps
Tidr	Input Delay Rise	0.3	2.5	ns
Tidf	Input Delay Fall	0.3	2.5	ns

Clock Timings

Symbol	Parameter	Minimum	Maximum	Unit	Notes	Figure
CLKOUT_PCIE_P/N[4:0]
Period	Period SSC On	9.849	10.201	ns		Figure: Measurement Points for Differential Waveforms
Period	Period SSC Off	9.849	10.151	ns		Figure: Measurement Points for Differential Waveforms
DtyCyc	Duty Cycle	40	60	%		Figure: Measurement Points for Differential Waveforms
V_Swing	Differential Output Swing	300	—	mV		Figure: Measurement Points for Differential Waveforms
Slew_rise	Rising Edge Rate	1.5	4	V/ns		Figure: Measurement Points for Differential Waveforms
Slew_fall	Falling Edge Rate	1.5	4	V/ns		Figure: Measurement Points for Differential Waveforms
	Jitter	—	150	ps	8, 9, 10
SSC	Spread Spectrum	0	0.5	%	11
SMBus/SMLink Clock (SMBCLK, SML0CLK)
fsmb	Operating Frequency	10	100	kHz		Figure: I2C, SMLink and SMBus Transaction
t18	High Time	4	50	µs	2
t19	Low Time	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20	Rise Time	—	1000	ns		Figure: I2C, SMLink and SMBus Transaction
t21	Fall Time	—	300	ns		Figure: I2C, SMLink and SMBus Transaction
SMLink[1,0] (SML0CLK) (Fast Mode: Refer note 15)
fsmb	Operating Frequency	0	400	kHz
t18_SMLFM	High Time	0.6	50	µs	2	Figure: I2C, SMLink and SMBus Transaction
t19_SMLFM	Low Time	1.3	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20_SMLFM	Rise Time	—	300	ns		Figure: I2C, SMLink and SMBus Transaction
t21_SMLFM	Fall Time	—	300	ns		Figure: I2C, SMLink and SMBus Transaction
SMLink[1,0] (SML0CLK) (Fast Mode Plus: Refer note 17)
fsmb	Operating Frequency	0	1000	kHz
t18_SMLFMP	High Time	0.26	—	µs	2	Figure: I2C, SMLink and SMBus Transaction
t19_SMLFMP	Low Time	0.5	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20_SMLFMP	Rise Time	—	120	ns		Figure: I2C, SMLink and SMBus Transaction
t21_SMLFMP	Fall Time	—	120	ns		Figure: I2C, SMLink and SMBus Transaction
I²C Clock (Standard Mode)
fsmb	Operating Frequency	0	100	kHz
t18_I2CSM	High Time	4	—	µs	2	Figure: I2C, SMLink and SMBus Transaction
t19_I2CSM	Low Time	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20_I2CSM	Rise Time	—	1000	ns		Figure: I2C, SMLink and SMBus Transaction
t21_I2CSM	Fall Time	—	300	ns		Figure: I2C, SMLink and SMBus Transaction
I²C Clock (Fast Mode)
fsmb	Operating Frequency	0	400	kHz
t18_I2CFM	High Time	0.6	—	µs	2	Figure: I2C, SMLink and SMBus Transaction
t19_I2CFM	Low Time	1.3	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20_I2CFM	Rise Time	20	300	ns		Figure: I2C, SMLink and SMBus Transaction
t21_I2CFM	Fall Time	20 x (V_DD/5.5 V)	300	ns		Figure: I2C, SMLink and SMBus Transaction
I²C Clock (Fast Mode Plus)
fsmb	Operating Frequency	0	1	MHz
t18_I2CFMP	High Time	0.26	—	µs	2	Figure: I2C, SMLink and SMBus Transaction
t19_I2CFMP	Low Time	0.5	—	µs		Figure: I2C, SMLink and SMBus Transaction
t20_I2CFMP	Rise Time	—	120	ns		Figure: I2C, SMLink and SMBus Transaction
t21_I2CFMP	Fall Time	20 x (V_DD/5.5 V)	120	ns		Figure: I2C, SMLink and SMBus Transaction
I²C Clock (High Speed Mode, Maximum Bus Capacitance (C_B) = 100 pF)
fsmb	Operating Frequency	0	3.4	MHz
t18_I2CHS1	High Time	60	—	ns	2	Figure: I2C, SMLink and SMBus Transaction
t19_I2CHS1	Low Time	160	—	ns		Figure: I2C, SMLink and SMBus Transaction
t20_I2CHS1	Rise Time	10	40	ns		Figure: I2C, SMLink and SMBus Transaction
t21_I2CHS1	Fall Time	10	40	ns		Figure: I2C, SMLink and SMBus Transaction
I²C Clock (High Speed Mode, Maximum Bus Capacitance (C_B) = 400 pF)
fsmb	Operating Frequency	0	1.7	MHz
t18_I2CHS2	High Time	120	—	ns	2	Figure: I2C, SMLink and SMBus Transaction
t19_I2CHS2	Low Time	320	—	ns		Figure: I2C, SMLink and SMBus Transaction
t20_I2CHS2	Rise Time	20	80	ns		Figure: I2C, SMLink and SMBus Transaction
t21_I2CHS2	Fall Time	20	80	ns		Figure: I2C, SMLink and SMBus Transaction
HDA_BLK (Intel® High Definition Audio)
f_HDA	Operating Frequency	24	—	MHz
	Frequency Tolerance	—	100	ppm
t26a	Input Jitter (refer to Clock Chip Specification)	—	300	ppm
t27a	High Time (Measured at 0.75 Vcc)	18.75	22.91	ns		Figure: Clock Timing
t28a	Low Time (Measured at 0.35 Vcc)	18.75	22.91	ns		Figure: Clock Timing
Suspend Clock (PMC_SUSCLK)
fsusclk	Operating Frequency	32		kHz	4
t39	High Time	9.5	—	µs	4
t39a	Low Time	9.5	—	µs	4
XTAL_IN/XTAL_OUT
ppm¹²	Crystal Tolerance cut accuracy maximum	35 ppm(@ 25 °C ±3 °C)
ppm¹²	Temp Stability Maximum	30 ppm(10 – 70 °C)
ppm¹²	Aging Maximum	5 ppm
Notes: N/A The maximum high time (t18 Max.) provide a simple ensured method for devices to detect bus idle conditions. BCLK Rise and Fall times are measured from 10% VDD and 90% VDD. SUSCLK duty cycle can range from 30% minimum to 70% maximum. Edge rates in a system as measured from 0.8 – 2.0 V. The active frequency can be 5 MHz, 50 MHz, or 62.5 MHz depending on the interface speed. Dynamic changes of the normal operating frequency are not allowed. Testing condition: 1 kOhm Pull-up to Vcc, 1 kOhm Pull-down and 10 pF Pull-down and 1/2 inch trace. Jitter is specified as cycle-to-cycle as measured between two rising edges of the clock being characterized. Period minimum and maximum includes cycle-to-cycle jitter and is also measured between two rising edges of the clock being characterized. On all jitter measurements care should be taken to set the zero crossing voltage (for rising edge) of the clock to be the point where the edge rate is the fastest. Using a Math function = Average(Derivative(Ch1)) and set the averages to 64, place the cursors where the slope is the highest on the rising edge—usually this lower half of the rising edge. The reason this is defined is for users trying to measure in a system it is impossible to get the probe exactly at the end of the Transmission line with large Flip-Chip components. This results in a reflection induced ledge in the middle of the rising edge and will significantly increase measured jitter. Phase jitter requirement: The designated outputs will meet the reference clock jitter requirements from the PCI Express Base Specification. The test is to be performed on a component test board under quiet conditions with all clock outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG. Measurement methodology is defined in the Intel document “PCI Express Reference Clock Jitter Measurements. This is not for ITPXDP_P/N. Spread Spectrum (SSC) is referenced to rising edge of the clock. Total of crystal cut accuracy, frequency variations due to temperature, parasitics, load capacitance variations and aging is recommended to be less than 90 ppm. Spread Spectrum (SSC) is referenced to rising edge of the clock. Spread Spectrum (SSC) of 0.25% on CLKOUT_PCIE[4:0] is used for WiMAX friendly clocking purposes. When SMLink[1,0] is configured to run in Fast Mode (FM) using a soft strap, the supported operating range is 0 Hz ~ 400 kHz, but the typical operating frequency is in the range of 300 kHz – 400 kHz. The 25 MHz output option for CLKOUTFLEX2 is derived from the 25 MHz crystal input to the PCH. The PPM of the 25 MHz output is equivalent to that of the crystal. When SMLink[1,0] is configured to run in Fast Mode Plus (FMP) using a soft strap, the supported operating range is 0 Hz ~ 1 MHz, but the typical operating frequency is in the range of 900 kHz – 1000 kHz. This is the default mode for this interface. Higher fall times are expected at High Speed mode. Validation data shows no functional failures with fall times as low as 9.4 ns and 8.3 ns on SDA and SCL respectively in High Speed mode at 3.3 V with Cb=100 pF.

Note:Refer to PCI Local Bus Specification for measurement details.

Clock Timing

Measurement Points for Differential Waveforms

USB 2.0 Timing

Sym	Parameter	Minimum	Maximum	Units	Notes	Figure
Full-speed Source (Note 7)
t100	USBPx+, USBPx- Driver Rise Time	4	20	ns	1,6 CL = 50 pF	Figure: USB Rise and Fall Times
t101	USBPx+, USBPx- Driver Fall Time	4	20	ns	1,6 CL = 50 pF	Figure: USB Rise and Fall Times
t102	Source Differential Driver Jitter - To Next Transition - For Paired Transitions	–3.5 –4	3.5 4	ns ns	2, 3	Figure: USB Jitter
t103	Source SE0 interval of EOP	160	175	ns	4	Figure: USB EOP Width
t104	Source Jitter for Differential Transition to SE0 Transition	–2	5	ns	5
t105	Receiver Data Jitter Tolerance - To Next Transition - For Paired Transitions	–18.5 –9	18.5 9	ns ns	3	Figure: USB Jitter
t106	EOP Width: Receiver must accept EOP	82	—	ns	4	Figure: USB EOP Width
t107	Width of SE0 interval during differential transition	—	14	ns
Low-Speed Source (Note 8)
t108	USBPx+, USBPx – Driver Rise Time	75	300	ns	1,6 CL = 200 pF CL = 600 pF	Figure: USB Rise and Fall Times
t109	USBPx+, USBPx – Driver Fall Time	75	300	ns	1,6 CL = 200 pF CL = 600 pF	Figure: USB Rise and Fall Times
t110	Source Differential Driver Jitter - To Next Transition - For Paired Transitions	–25 –14	25 14	ns ns	2,3	Figure: USB Jitter
t111	Source SE0 interval of EOP	1.25	1.5	µs	4	Figure: USB EOP Width
t112	Source Jitter for Differential Transition to SE0 Transition	–40	100	ns	5
t113	Receiver Data Jitter Tolerance - To Next Transition - For Paired Transitions	–152 –200	152 200	ns ns	3	Figure: USB Jitter
t114	EOP Width: Receiver must accept EOP	670	—	ns	4	Figure: USB EOP Width
t115	Width of SE0 interval during differential transition	—	210	ns
Notes: Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. Timing difference between the differential data signals. Measured at crossover point of differential data signals. Measured at 50% swing point of data signals. Measured from last crossover point to 50% swing point of data line at leading edge of EOP. Measured from 10% to 90% of the data signal. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.

USB 3.2 Interface Transmit and Receiver Timings

Sym	Parameter	USB 3.2 Gen 1x1 (5 Gb/s)		USB 3.2 Gen 2x1 (10 Gb/s)		Units
Sym	Parameter	Minimum	Maximum	Minimum	Maximum	Units
UI	Unit Interval	199.94	200.06	99.97	100.03	ps
T_TX-EYE	Minimum Transmission Eye Width	0.625	—	0.646	—	UI
PU3	Polling Period U3 State	—	100	—	100	mS
PRX-Detect	Polling Period Rx Detect	—	100	—	100	mS

USB Rise and Fall Times

USB Jitter

USB EOP Width

SATA Interface Timings

Symbol	Parameter	Minimum	Maximum	Units	Notes
UI-3	Gen III Operating Data Period (6 Gb/s)	166.6083	166.6667	ps
t120gen3	Rise Time	0.2	0.48	UI	1
t121gen3	Fall Time	0.2	0.48	UI	2
t122	TX differential skew	—	20	ps
t123	COMRESET	304	336	ns	3
t124	COMWAKE transmit spacing	101.3	112	ns	3
t125	OOB Operating Data period	646.67	686.67	ns	4
Notes: 20 – 80% at transmitter 80 – 20% at transmitter As measured from 100 mV differential crosspoints of last and first edges of burst Operating data period during Out-Of-Band burst transmissions

SMBus Timing

Sym	Parameter	Minimum	Maximum	Units	Notes	Figure
t130_{100 kHz}	Bus Free Time Between Stop and Start Condition	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t131_{100 kHz}	Hold Time after (repeated) Start Condition. After this period, the first clock is generated.	4	—	µs		Figure: I2C, SMLink and SMBus Transaction
t132_{100 kHz}	Repeated Start Condition Setup Time	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t133_{100 kHz}	Stop Condition Setup Time	4	—	µs		Figure: I2C, SMLink and SMBus Transaction
t134_{100 kHz}	Data Hold Time	0	—	ns		Figure: I2C, SMLink and SMBus Transaction
t135_{100 kHz}	Data Setup Time	250	—	ns		Figure: I2C, SMLink and SMBus Transaction
t136	Device Time Out	25	35	ms	1
t137	Cumulative Clock Low Extend Time (slave device)	—	25	ms	2	Figure: SMBus/SMLink Timeout
t138	Cumulative Clock Low Extend Time (master device)	—	10	ms	3	Figure: SMBus/SMLink Timeout
T_por	Time in which a device must be operational after power-on reset	—	500	ms
Notes: A device will timeout when any clock low exceeds this value. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop.

I²C and SMLink Timing

Sym²	Parameter	Minimum	Maximum	Units	Notes	Figure
t130_SM	Bus Free Time Between Stop and Start Condition	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t130_FM	Bus Free Time Between Stop and Start Condition	1.3	—	µs		Figure: I2C, SMLink and SMBus Transaction
t130_FMP	Bus Free Time Between Stop and Start Condition	0.5	—	µs		Figure: I2C, SMLink and SMBus Transaction
t131_SM	Hold Time after (repeated) Start Condition. After this period, the first clock is generated.	4	—	µs		Figure: I2C, SMLink and SMBus Transaction
t131_FM	Hold Time after (repeated) Start Condition. After this period, the first clock is generated.	0.6	—	µs		Figure: I2C, SMLink and SMBus Transaction
t131_FMP	Hold Time after (repeated) Start Condition. After this period, the first clock is generated.	0.26	—	µs		Figure: I2C, SMLink and SMBus Transaction
t131_HSM	Hold Time after (repeated) Start Condition. After this period, the first clock is generated.	160	—	ns		Figure: I2C, SMLink and SMBus Transaction
t132_SM	Repeated Start Condition Setup Time	4.7	—	µs		Figure: I2C, SMLink and SMBus Transaction
t132_FM	Repeated Start Condition Setup Time	0.6	—	µs		Figure: I2C, SMLink and SMBus Transaction
t132_FMP	Repeated Start Condition Setup Time	0.26	—	µs		Figure: I2C, SMLink and SMBus Transaction
t132_HSM	Repeated Start Condition Setup Time	160	—	ns		Figure: I2C, SMLink and SMBus Transaction
t133_SM	Stop Condition Setup Time	4	—	µs		Figure: I2C, SMLink and SMBus Transaction
t133_FM	Stop Condition Setup Time	0.6	—	µs		Figure: I2C, SMLink and SMBus Transaction
t133_FMP	Stop Condition Setup Time	0.26	—	µs		Figure: I2C, SMLink and SMBus Transaction
t133_HSM	Stop Condition Setup Time	160	—	ns		Figure: I2C, SMLink and SMBus Transaction
t134_SM	Data Hold Time	300	—	ns	1	Figure: I2C, SMLink and SMBus Transaction
t134_FM	Data Hold Time	0	—	ns		Figure: I2C, SMLink and SMBus Transaction
t134_FMP	Data Hold Time	0	—	ns		Figure: I2C, SMLink and SMBus Transaction
t135_SM	Data Setup Time	250	—	ns		Figure: I2C, SMLink and SMBus Transaction
t135_FM	Data Setup Time	100	—	ns		Figure: I2C, SMLink and SMBus Transaction
t135_FMP	Data Setup Time	50	—	ns		Figure: I2C, SMLink and SMBus Transaction
t135_HSM	Data Setup Time	10	—	ns		Figure: I2C, SMLink and SMBus Transaction
Notes: t134 has a minimum timing for SMLINK is 300 ns. Timings with the SM designator apply to I2C[0:5] and SMLink[1,0] when operating in Standard Mode, timings with the FM designator apply to I2C[0:5] and SMLink[1:0] when operating in Fast Mode, timings with the FMP designator apply to I2C[0:5] and SMLink[1:0] when operating in Fast Mode Plus and timing with the HSM designator apply only to I2C[0:5] when operating in High Speed Mode.

I²C, SMLink and SMBus Transaction

Note:txx also refers to txx_SMLFM and txx_SMLFMP, txxx also refers to txxxSMLFM and txxxSMLFMP, SMBCLK also refers to SML0CLK, and SMBDATA also refers to SML[1:0]DATA.

SMBus/SMLink Timeout

Note:In this image SMBCLK also refers to SML[1:0]CLK and SMBDATA also refers to SML[1:0]DATA.

Intel® High Definition Audio (Intel® HD Audio) Timing

Symbol	Parameter	Minimum	Maximum	Units	Figure
t143	Time duration for which HDA_SDO is valid before HDA_BCLK edge.	6.40	13.20(24 MHz) 40.00(12 MHz)	ns	Figure: Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings
t144	Time duration for which HDA_SDO is valid after HDA_BCLK edge.	6.40	13.20(24 MHz) 40.00(12 MHz)	ns	Figure: Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings
t145	Setup time for HDA_SDI[1:0] at rising edge of HDA_BCLK	20(24 MHz) 80(12 MHz)	—	ns	Figure: Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings
t146	Hold time for HDA_SDI[1:0] at rising edge of HDA_BCLK	3	—	ns	Figure: Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings

Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings

DMIC Timing

Symbol	Parameter	Minimum	Maximum	Units	Figure
	DMIC_DATA[0:1] Setup Time to DMIC_CLK[0:1] Rising	20	—	ns	Figure: Setup and Hold Times
	DMIC_DATA[0:1] Hold Time from DMIC_CLK[0:1] Rising	1	—	ns	Figure: Setup and Hold Times
Note:DMIC interface rise and fall times are characterized at the PCH package ball.

Intel® Pentium® Silver and Intel® Celeron® Processors

Datasheet, Volume 1 of 2