Jasper Lake EDS Vol1

Datasheet

ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents
DSP

Additional Voltage Rail Signals

There are additional voltage rail pins for routing power between parts of the processor and the platform listed in the table below.

Additional Voltage Rail Signals

Rail

Voltage

Description

VCCPLL

1.05 V

Processor PLL power rails

VCCST

1.05 V

Sustain voltage for processor

standby modes

VCC1P05_​OUT

1.05 V

FIVR Output of PCH to platform 1.05 V Power Gates

VCCSTG

1.05 V

Gated sustain voltage for processor standby modes

VCCSTG_​OUT

1.05 V

VCCSTG_​OUT Power rail

VCCLDOSTD_​0P85

0.85 V

This rail is generated internally and needs to be routed out to the motherboard for decoupling purpose.

VCCPRIM_​1P05

1.05 V

1.05 V Primary rail

VCCA_​CLKLDO_​1P8

1.8 V

Analog supply for internal clocks

VCCDPHY_​1P24

1.24 V

1.24 V rail for DPHY

VCCPGPPR

1.8 V / 3.3 V

VCC_​PGPPR is sourced from either VCC_​3P3A or VCC1P8A rail and this rail is input supply for the GP_​R GPIOs.

VCC1P8A

1.8 V

1.8A rail. This rail is turned off when either PMC_​CPU_​C10_​GATE_​N or PMC_​SLP_​S3_​N is asserted (LOW). Thus, this rail is off in package C10 state as well as S3 - S5 states.

VCCRTC

3 V

RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained.

Note:VCCRTC nominal voltage is 3.0 V. This rail is intended to always come up first and always stay on. It should NOT be power cycled regularly on non-coin battery designs. Note:Implementation should not attempt to clear CMOS by using a jumper to pull VCCRTC low. Clearing CMOS can be done by using a jumper on RTCRST# or GPI.

VCCPLL_​OC

1.1 V/1.2 V

Processor PLLs power rails

VCCSPI

3.3 V or 1.8 V

SPI Primary Well 3.3 V or 1.8 V. If powered at 3.3 V, the 3.3 V supply can come from VCCPRIM_​3P3 supply. If powered at 1.8 V, the 1.8 V supply can come from VCCPRIM_​1P8 supply.

VCCDSW_​3P3

3.3 V

3.3 V Deep Sx Well.