Power Management States Supported

Jasper Lake EDS Vol1

Datasheet

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ID 633935

Date 01/01/2021

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This section describes the ACPI states supported by the processor.

System Power States

This figure shows how the platform ACPI states work with the CPU C power states (package C-states) and the CPU P performance states.

The following table describes the Gx/Sx ACPI states.

System States

State	Description
G0/S0	Full On
G1/S3	Sleep/Suspend-to-RAM (STR). Context saved to memory
G1/S4	Suspend-to-Disk (STD). All power lost (except wake-up on PCH).
G2/S5	Soft off. All power lost (except wake-up on PCH). Total reboot.
G3	Mechanical off. All power removed from system.

The following table provides information on the IMC states.

Integrated Memory Controller (IMC) States

State	Description
Power up	CKE asserted. Active mode
Pre-charge Power down	CKE de-asserted (not self-refresh) with all banks closed
Active Power down	CKE de-asserted (not self-refresh) with minimum one bank active
Self-Refresh	CKE de-asserted using device self-refresh

The following table provides information on how the Global and Sleep states relate to the Processor states and system clocks.

G, S, and C Interface State Combinations

Global (G) State	Sleep (S) State	Processor Package (C) State	Processor State	System Clocks	Description
G0	S0	C0	Full On	On	Full On
G0	S0	C2	Deep Sleep	On	Deep Sleep
G0	S0	C3	Deep Sleep	On	Deep Sleep
G0	S0	C6/C7	Deep Power Down	On	Deep Power Down
G0	S0	C8	Off	On	Deeper Power Down
G0	S0ix	C10	Off	Off, except RTC	Enters S0ix
G1	S3	Power off	Off	Off, except RTC	Suspend to RAM
G1	S4	Power off	Off	Off, except RTC	Suspend to Disk
G2	S5	Power off	Off	Off, except RTC	Soft Off
G3	N/A	Power off	Off	Power off	Hard off

State Transition Rules for the PCH

Present State	Transition Trigger	Next State
G0/S0/C0	OPI Msg SLP_EN bit set Power Button Override³ Mechanical Off/Power Failure	G0/S0/Cx G1/Sx or G2/S5/S4 state G2/S5 G3
G0/S0/Cx	OPI Msg Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0 S5 G3
G1/S3	Any Enabled Wake Event Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0² G2/S5/S4 G3
G1/S4	Any Enabled Wake Event Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0² G2/S5 G3
G2/S5	Any Enabled Wake Event Mechanical Off/Power Failure	G0/S0/C0² G3
G3	Power Returns	S0/C0 (reboot) or G2/S5⁴ (stay off until power button pressed or other wake event)^1,2
Notes: Some wake events can be preserved through power failure. Transitions from the S3–S5 or G3 states to the S0 state are deferred until PMC_BATLOW_N is inactive in mobile configurations. Includes all other applicable types of events that force the host into and stay in G2/S5. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.

The System has several independent power planes as described in the table. When a particular power plane is shut off, it should go to a 0 V level.

System Power Plane

Plane	Controlled By	Description
CPU	PMC_SLP_S3_N signal	The PMC_SLP_S3_N signal is used to cut the power to the CPU completely.
Main (Applicable to Platform, PCH does not have a Main well)	PMC_SLP_S3_N signal	When PMC_SLP_S3_N goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, PCI Express* will typically be power-gated when the Main power plane is shut, although there may be small subsections powered. Note:The PCH power is not controlled by the PMC_SLP_S3_N signal, but instead by the PMC_SLP_SUS_N signal.
Device and Memory	PMC_SLP_S4_N signal PMC_SLP_S5_N signal	When PMC_SLP_S4_N goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When PMC_SLP_S5_N goes active, power can be shut off to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut.
Primary/ Suspend Well	PMC_SLP_SUS_N	This signal is asserted when the Primary/Suspend rails can be externally shut off for enhanced power saving
VCCIO_EXT	CPU_C10_GATE_N	This signal is asserted (LOW) when the processor enters C10 and can handle VCCIO_EXT,VCC1P8A, and VCCPLL_OC being lowered to 0V.
DEVICE[n]	Implementation Specific	Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen.