Jasper Lake EDS Vol1
Datasheet
DRAM Channel Support Matrix and Signals Terminology
| Number of DRAMs | DRAM Type | Sub-Channel Population |
|---|---|---|
| 2 | x32 | DRAM 0 is connected to Sub Channel A DRAM 1 is connected to Sub Channel B |
| 4 | x32 | DRAM 0 is connected to Sub Channel A DRAM 1 is connected to Sub Channel B DRAM 2 is connected to Sub Channel C DRAM 3 is connected to Sub Channel D |
| Memory Type | DDR4 SoDIMM (Per Channel) | LPDDR4/4x Memory Down (All Channels) |
|---|---|---|
| Signal details | ||
| Clock (CLK) | DDR_[1:0]_CLK[1:0]_DN, DDR_[1:0]_CLK[1:0]_DP | LP4x_[3:0]_CLK_DN, LP4x_[3:0]_CLK_DP |
| Control (CTRL) | DDR_[1:0]_CS[1:0]_N, DDR_[1:0]_ODT[1:0] | LP4x_0_CS0 LP4x_1_CS1 LP4x_2_CS0 LP4x_3_CS1 |
| Clock Enable (CKE) | DDR_[1:0]_CKE[1:0] | LP4x_0_CKE0 LP4x_1_CKE1 LP4x_2_CKE0 LP4x_3_CKE1 |
| Command (CMD) | DDR_[1:0]_MA[13:0], DDR_[1:0]_MA14_WE_N, DDR_[1:0]_MA15_CAS_N, DDR_[1:0]_MA16_RAS_N, DDR_[1:0]_BG[1:0], DDR_[1:0]_BA[1:0], DDR_[1:0]_ACT_N, DDR_[1:0]_PAR | LP4x_[3:0]_CA[5:0] |
| Alert | DDR_[1:0]_ALERT_N | N/A |
| Strobe | DDR_[1:0]_DQS[7:0]_DN, DDR_[1:0]_DQS[7:0]_DP | LP4x_[3:0]_DQS[3:0]_DN, LP4x_[3:0]_DQS[3:0]_DP |
| Data | DDR_[1:0]_DQ[63:0] | LP4x_[3:0]_DQ[31:0] |
| Reset | PMC_DRAM_RESET_N | PMC_DRAM_RESET_N |
| RCOMP | DDR_RCOMP[2:0] | LP4x_RCOMP[2:0] |
| Vref | DDR_[1:0]_VREF_CA | N/A |
| VTT | DDR_VTT_CTL | N/A |