DRAM Channel Support Matrix and Signals Terminology

Jasper Lake EDS Vol1

Download as PDF

ID 633935

Date 01/01/2021

Version

Public Content

A newer version of this document is available. Customers should click here to go to the newest version.

Number of DRAMs	DRAM Type	Sub-Channel Population
2	x32	DRAM 0 is connected to Sub Channel A DRAM 1 is connected to Sub Channel B
4	x32	DRAM 0 is connected to Sub Channel A DRAM 1 is connected to Sub Channel B DRAM 2 is connected to Sub Channel C DRAM 3 is connected to Sub Channel D

Number of DRAMs

DRAM Type

Sub-Channel Population

x32

DRAM 0 is connected to Sub Channel A

DRAM 1 is connected to Sub Channel B

x32

DRAM 0 is connected to Sub Channel A

DRAM 1 is connected to Sub Channel B

DRAM 2 is connected to Sub Channel C

DRAM 3 is connected to Sub Channel D

Memory Type	DDR4 SoDIMM (Per Channel)	LPDDR4/4x Memory Down (All Channels)
Signal details
Clock (CLK)	DDR_[1:0]_CLK[1:0]_DN, DDR_[1:0]_CLK[1:0]_DP	LP4x_[3:0]_CLK_DN, LP4x_[3:0]_CLK_DP
Control (CTRL)	DDR_[1:0]_CS[1:0]_N, DDR_[1:0]_ODT[1:0]	LP4x_0_CS0 LP4x_1_CS1 LP4x_2_CS0 LP4x_3_CS1
Clock Enable (CKE)	DDR_[1:0]_CKE[1:0]	LP4x_0_CKE0 LP4x_1_CKE1 LP4x_2_CKE0 LP4x_3_CKE1
Command (CMD)	DDR_[1:0]_MA[13:0], DDR_[1:0]_MA14_WE_N, DDR_[1:0]_MA15_CAS_N, DDR_[1:0]_MA16_RAS_N, DDR_[1:0]_BG[1:0], DDR_[1:0]_BA[1:0], DDR_[1:0]_ACT_N, DDR_[1:0]_PAR	LP4x_[3:0]_CA[5:0]
Alert	DDR_[1:0]_ALERT_N	N/A
Strobe	DDR_[1:0]_DQS[7:0]_DN, DDR_[1:0]_DQS[7:0]_DP	LP4x_[3:0]_DQS[3:0]_DN, LP4x_[3:0]_DQS[3:0]_DP
Data	DDR_[1:0]_DQ[63:0]	LP4x_[3:0]_DQ[31:0]
Reset	PMC_DRAM_RESET_N	PMC_DRAM_RESET_N
RCOMP	DDR_RCOMP[2:0]	LP4x_RCOMP[2:0]
Vref	DDR_[1:0]_VREF_CA	N/A
VTT	DDR_VTT_CTL	N/A

	DDR max rate [MT/s]	SAGV-Low DDR CLK, Gear	SAGV-Mid DDR CLK, Gear	SAGV-High DDR CLK, Gear
DDR4	2133	2133,G2	2133,G2	2133,G2
	2400	2133,G2	2400,G2	2400,G2
	2666	2133,G2	2400,G2	2666,G2
	2933	2133,G2	2400,G2	2933,G2
LPDDR4/x	2133	2133,G2	2133,G2	2133,G2
	2400	2133,G2	2400,G2	2400,G2
	2666	2133,G2	2400,G2	2666,G2
	2933	2133,G2	2400,G2	2933,G2
Notes: Intel^® Pentium^® Silver and Intel^® Celeron^® Processor supports dynamic gearing technology where the Memory Controller can run at 1:2 (Gear-2 mode)ratio of DRAM speed. Gear ratio is the ratio of DRAM speed to Memory Controller Clock. MC Channel Width equal to DDR Channel width multiply by Gear Ratio. SA-GV modes: Low- Low frequency point, Min Power point. Characterized by low power, low BW, high latency. System will stay at this point during low to moderate BW consumption. Mid - Max Bandwidths Point, this point is the max possible BW point, the DRAM freq limited by Silicon Configuration/BIOS/SPD. Characterized by moderate power and latency, high BW. This point intended for high GT and moderate-high IA BW High - High Point, the minimum memory latency point, Characterized by high power, low latency, moderate BW. Only during IA performance workloads the system will to switch to this point and only in case this point can provide enough BW.