Jasper Lake EDS Vol1

Datasheet

ID 633935
Date 01/01/2021
Public Content

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
DSP

CPU Core Overview

Category

Feature Description

CPU Cores

Quad/Dual IA ATOM Core

  • 3-way Superscalar, Out of Order Execution (OOE)
  • 10 nm CPU technology

Modules/Caches

  • 1 set of 2 cores (for Dual Core) or 2 set of 2 cores (for Quad Core)
  • On-die, parity protected 32KB 8-way (64 sets) L1 instruction cache and 32KB 8-way (64 sets) L1 data cache per core
  • On-die, 12-way (2048 sets) L2 unified cache for all cores(module)

Architecture

Intel® 64-bit

Virtualization Architecture

Intel® Virtualization Technology

  • VTx-2 with Extended Page Table
  • VT-d

Burst Technology

1/2/3/4 Core Burst Technology

  • All cores in C0 state runs at the same frequency

Thermal Management

Supported by means of Intel® Thermal Monitor (TM1 and TM2)

Power Management

  • Enhanced Intel SpeedStep® Technology and Intel® Speed Shift Technology
  • Core C-States: C0, C1, C1E, C6, C6S, C7,C8,C10
  • Module C-States: MC0, MC6

Other features

Security Technologies:

  • Branch Monitoring Counters, Intel® AES-NI, PCLMULQD, Execute Disable Bit, Boot Guard, Intel® SMEP, Intel® SMAP, Intel® SHA Extensions, User Mode Instruction Prevention, Read Processor ID.

Power and Performance Technologies:

  • x2APIC, Cache Line Write Back

Debug Technologies:

  • Intel® Processor Trace