Jasper Lake EDS Vol1


ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents

Open Chassis Debug

MIPI-60 Debug Port is available for Open Chassis Debug access. The MIPI-60 JTAG topology is “Merged-Parallel”, the CPU and PCH JTAG signals share common connector pins, except for TCKs, for which there are two dedicated pins. It consists of JTAG (TAP), CPU Run-control, PTI CFG (To correlate and be consistent as mentioned in Intel® Trace Hub) and other miscellaneous signals such as DFx hard-straps, system status, triggers in/out, reset generation, power controls. Lauterbach and TRACE32 are the debug tool set supported via MIPI-60 Debug Port. The TRACE 32 debugger allows to test embedded hardware and software.