Jasper Lake EDS Vol1

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ID 633935
Date 01/01/2021
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Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory Graphics Display Imaging Pin Strap General Purpose Input and Output (GPIO) PCH Electrical Specification CPU Electrical Specifications Global Device IDs CPU And Device IDs Audio, Voice, and Speech Connectivity Integrated (CNVi) PCI Express* (PCIe*) Universal Serial Bus (USB) Serial ATA (SATA) Flexible I/O Storage Serial Peripheral Interface (SPI) Intel® Serial I/O Generic SPI (GSPI) Controllers Enhanced Serial Peripheral Interface (eSPI) Real Time Clock (RTC) 8254 Timers High Precision Event Timer (HPET) Intel® LPSS Inter-Integrated Circuit (I2C) Controllers Host System Management Bus (SMBus) Controller System Management Interface and SMLink System Management Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Testability SoC Pin Location
Legal Disclaimer
Revision History
Introduction
Introduction Block Diagram CPU Core Overview Features Supported SKUs
Block Diagram
CPU Core Overview
Features Supported
SKUs
Technologies
Technologies Security Technologies Power and Performance Technologies Debug Technologies Intel® Debug and Tool References
Security Technologies
Security Technologies Branch Monitoring Counters Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection (SMEP) Intel® Supervisor Mode Access Protection (SMAP) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID)
Branch Monitoring Counters
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Power and Performance Technologies
Power and Performance Technologies Intel® Smart Cache Technology IA Core Level 1 and Level 2 Caches Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology Intel ® 64 Architecture x2APIC Cache Line Write Back (CLWB) Converged Audio Voice Speech (cAVS) Integrated Connectivity (CNVi)
Intel® Smart Cache Technology
IA Core Level 1 and Level 2 Caches
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel ® 64 Architecture x2APIC
Cache Line Write Back (CLWB)
Converged Audio Voice Speech (cAVS)
Integrated Connectivity (CNVi)
Debug Technologies
Debug Technologies Intel® Processor Trace JTAG Intel® Trace Hub Intel® Direct Connect Interface (DCI)
Intel® Processor Trace
JTAG
Intel® Trace Hub
Intel® Direct Connect Interface (DCI)
Intel® Debug and Tool
Intel® Debug and Tool Open Chassis Debug Closed Chassis Debug
Open Chassis Debug
Closed Chassis Debug
References
Power Management
Power Management Power Management States Supported Processor IA Core Power Management PM Interface Signals Processor Voltage Rails Voltage Rail Electrical Specifications
Power Management States Supported
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting Low-Power Idle States Processor IA Core C-State Rules Package C-States Exiting Sleep States
OS/HW Controlled P-states
Low-Power Idle States
Requesting Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Exiting Sleep States
PM Interface Signals
Processor Voltage Rails
Processor Voltage Rails Fully Integrated Voltage Regulator (FIVR) Main Platform Voltage Regulators Additional Voltage Rail Signals VCCIN_AUX External Bypass Rails (VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05)
Fully Integrated Voltage Regulator (FIVR)
Main Platform Voltage Regulators
Additional Voltage Rail Signals
VCCIN_AUX
External Bypass Rails (VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05)
Voltage Rail Electrical Specifications
Voltage Rail Electrical Specifications Processor Power Rails DC Specifications
Processor Power Rails DC Specifications
Thermal Management
Thermal Management Thermal and Power Specifications Processor Thermal Management PCH Thermal Management
Thermal and Power Specifications
Processor Thermal Management
Processor Thermal Management Thermal Considerations Thermal Management Features Intel® Memory Thermal Management
Thermal Considerations
Thermal Management Features
Intel® Memory Thermal Management
PCH Thermal Management
PCH Thermal Management PCH Thermal Sensor Modes of Operation Thermal Reporting to an External Device Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Trip Signal (PCHHOT_N)
PCH Thermal Sensor
Modes of Operation
Thermal Reporting to an External Device
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Trip Signal (PCHHOT_N)
Memory
Memory System Memory Interface Power Management
System Memory Interface
System Memory Interface DRAM Channel Support Matrix and Signals Terminology Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping DRAM Clock Generation DRAM Reference Voltage Generation
DRAM Channel Support Matrix and Signals Terminology
Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
DRAM Clock Generation
DRAM Reference Voltage Generation
Power Management
Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DDR Electrical Power Gating
Power Training
Graphics
Graphics Processor Graphics
Processor Graphics
Processor Graphics Graphic Features Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode and Encode
Graphic Features
Media Support (Intel® QuickSync and Clear Video Technology HD)
Hardware Accelerated Video Decode and Encode
Display
Display General Capabilities Features Supported Port Configuration SoC Display Architecture Display Interfaces High-Bandwidth Digital Content Protection (HDCP) Display Technologies
General Capabilities
Features Supported
Port Configuration
SoC Display Architecture
Display Interfaces
High-Bandwidth Digital Content Protection (HDCP)
Display Technologies
Display Technologies DisplayPort High-Definition Multimedia Interface (HDMI) Embedded DisplayPort (eDP*) MIPI DSI More Features of Display Controller Integrated Audio
DisplayPort
High-Definition Multimedia Interface (HDMI)
Embedded DisplayPort (eDP*)
MIPI DSI
More Features of Display Controller
Integrated Audio
Imaging
Imaging DPHY and CSI Controller Support Image Processing Capabilities
DPHY and CSI Controller Support
DPHY and CSI Controller Support Camera Connectivity Combinations Signal Description
Camera Connectivity Combinations
Signal Description
Image Processing Capabilities
Pin Strap
General Purpose Input and Output (GPIO)
General Purpose Input and Output (GPIO) Signal Description Functional Description
Signal Description
Functional Description
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation via SD3_RCOMP Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO (TIME_SYNC) GPIO Blink (BK) and Serial Blink (SBK) Interrupt / IRQ via GPIO Requirement Native Function and TERM Bit Setting Virtual GPIO (vGPIO)
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation via SD3_RCOMP
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO (TIME_SYNC)
GPIO Blink (BK) and Serial Blink (SBK)
Interrupt / IRQ via GPIO Requirement
Native Function and TERM Bit Setting
Virtual GPIO (vGPIO)
PCH Electrical Specification
PCH Electrical Specification Absolute Maximum Ratings General DC Characteristics AC Characteristics Overshoot/Undershoot Guidelines
Absolute Maximum Ratings
General DC Characteristics
AC Characteristics
AC Characteristics Panel Power Sequencing and Backlight Control
Panel Power Sequencing and Backlight Control
Overshoot/Undershoot Guidelines
CPU Electrical Specifications
CPU Electrical Specifications DC Specifications
DC Specifications
DC Specifications Display Port* Specification HDMI* Specifications embedded Display Port* Specifications 16550 8-bit Addressing - Debug Driver Compatibility MIPI* DSI Specification Memory Specifications MIPI* CSI Specifications CMOS DC Specifications GTL and Open Drain DC Specification PECI DC Characteristics
Display Port* Specification
HDMI* Specifications
embedded Display Port* Specifications
16550 8-bit Addressing - Debug Driver Compatibility
MIPI* DSI Specification
Memory Specifications
MIPI* CSI Specifications
CMOS DC Specifications
GTL and Open Drain DC Specification
PECI DC Characteristics
Global Device IDs
Global Device IDs PCH Global Device IDs PCH ACPI IDs Compute Global Device ID
PCH Global Device IDs
PCH ACPI IDs
Compute Global Device ID
CPU And Device IDs
Audio, Voice, and Speech
Audio, Voice, and Speech Features Supported Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Direct Attached Digital Microphone (PDM) Interface I2S/PCM Interface Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States References
Features Supported
Features Supported DSP Memory I/O Peripheral
DSP
Memory
I/O Peripheral
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities
Audio DSP Capabilities
Direct Attached Digital Microphone (PDM) Interface
I2S/PCM Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
References
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Features Supported Signal Description Integrated Pull-ups and Pull-downs Platform PU/PD Requirements I/O Signal Planes and States Functional Description
Features Supported
Signal Description
Integrated Pull-ups and Pull-downs
Platform PU/PD Requirements
I/O Signal Planes and States
Functional Description
PCI Express* (PCIe*)
PCI Express* (PCIe*) Features Supported Signal Description I/O Signal Planes and States PCI Express* Port / Controller Mapping
Features Supported
Features Supported Interrupt Generation PCI Express* Power Management Dynamic Link Throttling Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single- Root I/O Virtualization (SR- IOV) SERR# Generation Hot-Plug PCI Express* Lane Polarity Inversion PCI Express* Controller Lane Reversal Precision Time Measurement (PTM)
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single- Root I/O Virtualization (SR- IOV)
SERR# Generation
Hot-Plug
PCI Express* Lane Polarity Inversion
PCI Express* Controller Lane Reversal
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Port / Controller Mapping
Universal Serial Bus (USB)
Universal Serial Bus (USB) Features Supported USB Controllers Overview Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Features Supported
USB Controllers Overview
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Serial ATA (SATA)
Serial ATA (SATA) Signals Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signals Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description SATA 6 Gb/s Support SATA Feature Support Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation
SATA 6 Gb/s Support
SATA Feature Support
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Flexible I/O
Flexible I/O Flexible I/O Lane Selection
Flexible I/O Lane Selection
Storage
Storage embedded Multi Media Card (eMMC*) I/O Signal Planes and States Secure Digital (SD) I/O Signal Planes and States
embedded Multi Media Card (eMMC*)
embedded Multi Media Card (eMMC*) Features Supported eMMC Signals Description
Features Supported
eMMC Signals Description
I/O Signal Planes and States
I/O Signal Planes and States Functional Description
Functional Description
Secure Digital (SD)
Secure Digital (SD) SDXC Signal Description
SDXC Signal Description
I/O Signal Planes and States
I/O Signal Planes and States Features Supported Functional Description
Features Supported
Functional Description
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description FSPI for Flash FSPI Support for TPM
FSPI for Flash
FSPI Support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Generic SPI (GSPI) Controllers
Intel® Serial I/O Generic SPI (GSPI) Controllers Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
I/O Signal Planes and States Operating Frequency Protocols WAIT States from eSPI Slave In-Band Link Reset Slave Discovery PECI Over eSPI Multiple OOB Master Channels and Supported Transactions
Operating Frequency
Protocols
WAIT States from eSPI Slave
In-Band Link Reset
Slave Discovery
PECI Over eSPI
Multiple OOB Master
Channels and Supported Transactions
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
8254 Timers
8254 Timers Timer Programming Reading from the Interval Timer
Timer Programming
Reading from the Interval Timer
Reading from the Interval Timer Simple Read Counter Latch Command Read Back Command
Simple Read
Counter Latch Command
Read Back Command
High Precision Event Timer (HPET)
High Precision Event Timer (HPET) References Timer Accuracy Timer Off-load Interrupt Mapping Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels Handling Interrupts Issues Related to 64-Bit Timers with 32-Bit Processors
References
Timer Accuracy
Timer Off-load
Interrupt Mapping
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
Handling Interrupts
Issues Related to 64-Bit Timers with 32-Bit Processors
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers Signal Description I/O Signal Planes and States Functional Description
Signal Description
I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Slave Interface
Host Controller
SMBus Slave Interface
SMBus Power Gating
System Management Interface and SMLink
System Management Interface and SMLink Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation TCO Modes
TCO Modes
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Signal Description I/O Signal Planes and States Functional Description
Signal Description
I/O Signal Planes and States
Functional Description
Functional Description UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Testability
Testability Intel® Trace Hub (Intel® TH) Direct Connect Interface (DCI)
Intel® Trace Hub (Intel® TH)
Intel® Trace Hub (Intel® TH) Platform Setup
Platform Setup
Direct Connect Interface (DCI)
Direct Connect Interface (DCI) Out Of Band (OOB) Hosting DCI USB 3.2 Hosting DCI.DBC Platform Setup
Out Of Band (OOB) Hosting DCI
USB 3.2 Hosting DCI.DBC
Platform Setup
SoC Pin Location
Legal Disclaimer
Revision History
Introduction
Technologies
Power Management
Thermal Management
Memory
Graphics
Display
Imaging
Pin Strap
General Purpose Input and Output (GPIO)
PCH Electrical Specification
CPU Electrical Specifications
Global Device IDs
CPU And Device IDs
Audio, Voice, and Speech
Connectivity Integrated (CNVi)
PCI Express* (PCIe*)
Universal Serial Bus (USB)
Serial ATA (SATA)
Flexible I/O
Storage
Serial Peripheral Interface (SPI)
Intel® Serial I/O Generic SPI (GSPI) Controllers
Enhanced Serial Peripheral Interface (eSPI)
Real Time Clock (RTC)
8254 Timers
High Precision Event Timer (HPET)
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers
Host System Management Bus (SMBus) Controller
System Management Interface and SMLink
System Management
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Testability
SoC Pin Location

WAIT States from eSPI Slave

There are situations when the slave cannot predict the length of the command packet from the master (PCH). For non-posted transactions, the slave is allowed to respond with a limited number of WAIT states.

A WAIT state is a 1-byte response code. They must be the first set of response byte from the slave after the TAR cycles.

In-Band Link Reset