Jasper Lake EDS Vol1


ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents

DMA Controller

The GSPI controllers have an integrated DMA controller.

DMA Transfer and Setup Modes

The DMA can operate in the following modes:

  1. Memory to Peripheral Transfers. This mode requires that the peripheral control the flow of the data to itself.
  2. Peripheral to Memory Transfer. This mode requires that the peripheral control the flow of the data from itself.

The DMA supports the following modes for programming:

  1. Direct Programming: Direct register writes to DMA registers to configure and initiate the transfer.
  2. Descriptor based Linked List: The descriptors will be stored in memory. The DMA will be informed with the location information of the descriptor. DMA initiates reads and programs its own register. The descriptors can form a linked list for multiple blocks to be programmed.
  3. Scatter Gather mode

Channel Control

  • The source transfer width and destination transfer width are programmable. The width can be programmed to 1, 2, or 4 bytes.
  • Burst size is configurable per channel for source and destination. The number is a power of 2 and can vary between 1,2,4,...,128. this number times the transaction width gives the number of bytes that will be transferred per burst.
  • Individual Channel enables. If the channel is not being used, then it should be clock gated.
  • Programmable Block size and Packing/Unpacking. Block size of the transfer is programmable in bytes. the block size is not limited by the source or destination transfer widths.
  • Address incrementing modes: The DMA has a configurable mechanism for computing the source and destination addresses for the next transfer within the current block. The DMA supports incrementing addresses and constant addresses.
  • Flexibility to configure any hardware handshake sideband interface to any of the DMA channels.
  • Early termination of a transfer on a particular channel.