Jasper Lake EDS Vol1

Datasheet

ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents
DSP

Processor Power Rails DC Specifications

VccIN DC Specifications

Processor VccIN Active and Idle Mode DC Voltage and Current Specifications

Symbol

Parameter

Segment

Min

Typ

Max

Unit

Note1

Operating Voltage

Voltage Range for Processor Operating Mode

All

0

1.8

2

V

1,2,3, 7,11

IccMAX

Maximum

Processor

ICC

4 Core(6 W)

33

A

4,6,7,10

2 Core(6 W)

22

A

4 Core(10 W)

35

A

2 Core(10 W)

25

A

IccTDP

Thermal Design Current for processor VccIN Rail

10

A

TOBVCC

Voltage Tolerance

PS0,PS1

±20

mV

3, 6, 8

PS2,PS3

±35

Ripple

Ripple Tolerance

PS0,PS1

±15

mV

3, 6, 8

PS2,PS3

±30

DC_​LL

Loadline slope within the VR regulation loop capability

0

2

9,12,13

AC_​LL

AC Loadline (<10 MHz)

5

9,12,13

VOS

Max Overshoot Voltage

200

mV

T_​OVS_​TDP_​MAX

Max Overshoot time

TDP/virus mode

500

μs

V_​OVS TDP_​MAX/virus_​MAX

Max Overshoot at TDP/virus mode

10

%

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or low-power states).
  3. The voltage specification requirements are measured across Vcc_​SENSE and Vss_​SENSE as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
  4. Processor VccIN VR to be designed to electrically support this current.
  5. Processor VccIN VR to be designed to thermally support this current indefinitely.
  6. Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
  7. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
  8. PSx refers to the voltage regulator power state as set by the SVID protocol.
  9. LL measured at sense points.
  10. Typ column represents IccMAX for commercial application it is NOT a specification - it is a characterization of limited samples using limited set of benchmarks that can be exceeded.
  11. Operating voltage range in steady state.
  12. LL spec values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
  13. Load Line (AC/DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override setup options. AC/DC Load Line BIOS programming directly affects operating voltages (AC) and power measurements (DC). A superior board design with a shallower AC Load Line can improve on power, performance and thermals.

VCC1P8A DC Specifications

Processor VCC1P8A Supply DC Voltage and Current Specifications 

Symbol

Parameter

Min

Typ

Max

Unit

Notes1,2

Vcc1p8A

Package voltage (DC + AC specification)

1.8

V

1,3

IccMAX_​1p8A

Max Current for Vcc1p8A Rail

0.7

A

1

Iccidle

Sx Icc Idle Current

100

mA

TOB Vcc1p8A

Vcc1p8A Tolerance

AC+DC=+/-5%

%

1,3

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
  3. The voltage specification requirements are measured on package pins as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

VccIN_​AUX DC Specifications

VccIN_​AUX Supply DC Voltage and Current Specifications 

Symbol

Parameter

Min

Typ

Max

Unit

Note1

Vccin_​AUX

0

1.8

V

1,3,4

IccMAX

Maximum VccIN_​AUX Icc

0

24

A

1,10

Iccidle

Sx Icc Idle Current

0

201

mA

IccTDP

Thermal Design Current for processor VccIN_​Aux Rail

4

A

TOBVCC

Voltage Tolerance Budget

AC+DC: -10/+5

%

1,3,6

VOS

Overshoot Voltage

1.95

V

7

TVOS

Overshoot Time

500

us

7

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
  3. The voltage specification requirements are measured on package pins as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
  4. Max impedance allowed between 1 MHz-40 MHz is lower than LL3. Comply with recommended impedance target to avoid coupling noise concerns
  5. The LL3 values are for reference. must still meet voltage tolerance specification.
  6. Voltage Tolerance budget values Includes ripples
  7. Overshoot with max voltage of 2.13 V is allowed if it sustained for less then 500 us.
  8. This rail can be connect to 1.65 V
  9. The ICCMAX values combine power pins that feed the compute die and the PCH die in the processor.

VDDQ DC Specifications

Memory Controller (VDDQ) Supply DC Voltage and Current Specifications 

Symbol

Parameter

Min

Typ

Max

Unit

Note1

VDDQ (LPDDR4/x)

Processor I/O supply voltage for LPDDR4/x

-

1.1 (+/-5%)

-

V

3,4,5

VDDQ (DDR4)

Processor I/O supply voltage for DDR4

-

1.2 (+/-5%)

-

V

3,4,5

TOBVDDQ

VDDQ Tolerance

AC+DC:± 5%

%

3,4

IccMAX_​VDDQ (LPDDR4/x)

Max Current for VDDQ Rail (LPDDR4/x)

3.5

A

2

IccMAX_​VDDQ (DDR4)

Max Current for VDDQ Rail

(DDR4)

3.5

A

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. The current supplied to the DRAM is not included in this specification.
  3. Includes AC and DC error, where the AC noise is bandwidth limited to under 100 MHz, measured on package pins.
  4. No requirement on the breakdown of AC versus DC noise.
  5. The voltage specification requirements are measured on package pins as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MO minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

Additional Rails DC Characteristics

Additional Rails Estimated Icc

Voltage Rail

V Min

V Typical (V)

V Max

Iccmax Current1 (A)

Sx Iccmax Current (mA)

Sx Icc Idle Current (mA)

Deep Sx Icc Idle Current (mA)

G3

(uA)

VCCIO_​EXT3

0.98

1

1.02

5

-

-

-

-

VCCST

0.97

1.05

1.07

0.6

-

-

-

-

VCCSTG

0.97

1.05

1.07

0.15

-

-

-

-

VCCPLL

0.97

1.05

1.07

0.1

-

-

-

-

VCCPLL_​OC - 1.1/1.2 - 0.1

-

-

-

-

VCC_​VNNEXT_​1P05

-

1.05

-

0.2

150

0

-

-

VCC_​V1P05EXT_​1P05

-

1.05

-

0.2

150

0

-

-

VCCPGPPR

-

1.8

-

0.000237

0.17437

0

-

-

VCCA_​CLKLDO_​1P8

-

1.8

-

0.12

7.83135

2.965083

-

-

VCCPRIM_​1P8

-

1.8

-

1.3

619.379

124.8817

-

-

VCCPRIM_​3P3

-

3.3

-

0.232

0.92362

0.260667

-

-

VCCRTC

-

3.3

-

0.001

2

0.605318

0.339

6

VCCDSW_​3P3

-

3.3

-

0.001

0.32315

0.293773

2

-

Notes:
  1. Iccmax estimates assumes IPs are working at Vmax with 100% activity at 105°C.
  2. The Iccmax value is a steady state current that can happen after respective power ok has asserted (or reset signal has de-asserted).
  3. VCCIO_​EXT voltage tolerance is +/-5% for (DC+AC) & 2% only for DC