Jasper Lake EDS Vol1
Datasheet
ID | Date | Version | Classification |
---|---|---|---|
633935 | 01/01/2021 | Public Content |
A newer version of this document is available. Customers should click here to go to the newest version.
Legal Disclaimer
Revision History
Introduction
Technologies
Power Management
Thermal Management
Memory
Graphics
Display
Imaging
Pin Strap
General Purpose Input and Output (GPIO)
PCH Electrical Specification
CPU Electrical Specifications
Global Device IDs
CPU And Device IDs
Audio, Voice, and Speech
Connectivity Integrated (CNVi)
PCI Express* (PCIe*)
Universal Serial Bus (USB)
Serial ATA (SATA)
Flexible I/O
Storage
Serial Peripheral Interface (SPI)
Intel® Serial I/O Generic SPI (GSPI) Controllers
Enhanced Serial Peripheral Interface (eSPI)
Real Time Clock (RTC)
8254 Timers
High Precision Event Timer (HPET)
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers
Host System Management Bus (SMBus) Controller
System Management Interface and SMLink
System Management
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Testability
SoC Pin Location
Security Technologies
Branch Monitoring Counters
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word (PCLMULQDQ) Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation via SD3_RCOMP
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO (TIME_SYNC)
GPIO Blink (BK) and Serial Blink (SBK)
Interrupt / IRQ via GPIO Requirement
Native Function and TERM Bit Setting
Virtual GPIO (vGPIO)
DC Specifications
Display Port* Specification
HDMI* Specifications
embedded Display Port* Specifications
16550 8-bit Addressing - Debug Driver Compatibility
MIPI* DSI Specification
Memory Specifications
MIPI* CSI Specifications
CMOS DC Specifications
GTL and Open Drain DC Specification
PECI DC Characteristics
Features Supported
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single- Root I/O Virtualization (SR- IOV)
SERR# Generation
Hot-Plug
PCI Express* Lane Polarity Inversion
PCI Express* Controller Lane Reversal
Precision Time Measurement (PTM)
DMA Controller
The UART controllers 0 and 1 (UART0 and UART1) have an integrated DMA controller. Each channel contains a 64-byte FIFO. Max. burst size supported is 32 bytes.
UART controller 2 (UART2) only implements the host controllers and does not incorporate a DMA. Therefore, UART2 is restricted to operate in PIO mode only.
DMA Transfer and Setup Modes
The DMA can operate in the following modes:
- Memory to Peripheral Transfers: This mode requires that the peripheral control the flow of the data to itself.
- Peripheral to Memory Transfer: This mode requires that the peripheral control the flow of the data from itself.
The DMA supports the following modes for programming:
- Direct Programming: Direct register writes to DMA registers to configure and initiate the transfer.
- Descriptor based Linked List: The descriptors will be stored in memory (such as DDR or SRAM). The DMA will be informed with the location information of the descriptor. DMA initiates reads and programs its own register. The descriptors can form a linked list for multiple blocks to be programmed.
- Scatter Gather Mode
Channel Control
- The source transfer width and destination transfer width are programmable. It can vary to 1 byte, 2 bytes, and 4 bytes.
- Burst size is configurable per channel for source and destination. The number is a power of 2 and can vary between 1,2,4,...,128. this number times the transaction width gives the number of bytes that will be transferred per burst.
- Individual Channel enables. If the channel is not being used, then it should be clock gated.
- Programmable Block size and Packing/Unpacking. Block size of the transfer is programmable in bytes. the block size is not be limited by the source or destination transfer widths.
- Address incrementing modes: The DMA has a configurable mechanism for computing the source and destination addresses for the next transfer within the current block. The DMA supports incrementing addresses and constant addresses.
- Flexibility to configure any hardware handshake sideband interface to any of the DMA channels.
- Early termination of a transfer on a particular channel.