Jasper Lake EDS Vol1


ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents

Functional Description

The main blocks of the integrated Connectivity solution are partitioned according to the following:

  • Connectivity Controller IP contains:
    • Interfaces to the PCH
    • Debug and testing interfaces
    • Power management and clock Interfaces
    • Interface to the Companion RF module (CRF)
    • Interface to physical I/O pins controlled by the PCH
    • Interfaces to the LTE modem via PCH GPIO
  • Companion RF (CRF): This is the integrated connectivity M.2 module. The CRF Top contains:
    • Debug and testing interfaces
    • Power and clock Interfaces
    • Interface to the Connectivity Controller chip
  • Physical I/O pins: The SCU units are responsible for generating and controlling the power and clock resources of Connectivity Controller and CRF. There are unique SCUs in Connectivity Controller and CRF and their operation is coordinated due to power and clock dependencies. This coordination is achieved by signaling over a control bus (AUX) connecting Connectivity Controller and CRF.

Both Connectivity Controller and CRF have a dedicated AUX bus and arbiter. These two AUX buses are connected by a special interface that connects over the RGI bus. Each of the Connectivity Controller and CRF cores is dedicated to handle a specific connectivity function (Wi-Fi*, Bluetooth*).

Only the digital part of the connectivity function is located in Connectivity Controller cores, while the CRF cores handle some digital, but mostly analog and RF functionality. Each core in the Connectivity Controller has an interface to the host and an interface to its counterpart in CRF. CRF cores include an analog part which is connected to board level RF circuitry and to an antenna.