Enhanced Intel SpeedStep® Technology

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Introduction
Technologies
Power Management
Thermal Management
Memory
- System Memory Interface
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Graphics
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Imaging
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  - Camera Connectivity Combinations
  - Signal Description
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Pin Strap
General Purpose Input and Output (GPIO)
- Signal Description
- Functional Description
PCH Electrical Specification
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- DC Specifications
Global Device IDs
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Connectivity Integrated (CNVi)
PCI Express* (PCIe*)
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Flexible I/O
- Flexible I/O Lane Selection
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Serial Peripheral Interface (SPI)
Intel® Serial I/O Generic SPI (GSPI) Controllers
Enhanced Serial Peripheral Interface (eSPI)
Real Time Clock (RTC)
- Signal Description
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8254 Timers
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High Precision Event Timer (HPET)
Intel® LPSS Inter-Integrated Circuit (I2C) Controllers
Host System Management Bus (SMBus) Controller
System Management Interface and SMLink
- Signal Description
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System Management
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  - TCO Modes
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Testability
- Intel® Trace Hub (Intel® TH)
  - Platform Setup
- Direct Connect Interface (DCI)
SoC Pin Location

Enhanced Intel SpeedStep^® Technology enables OS to control and select P-state. The following are the key features of Enhanced Intel SpeedStep^® Technology:

Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states.
Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor IA cores.
- Once the voltage is established, the PLL locks on to the target frequency.
- All active processor IA cores share the same frequency and voltage. In a multi-core processor, the highest frequency P-state requested among all active IA cores is selected.
- Software-requested transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition is completed.
The processor controls voltage ramp rates internally to ensure glitch-free transitions.

Note: Because there is low transition latency between P-states, a significant number of transitions per-second are possible. All of Processor Cores must be in the same P-state at any given time.

Intel® Speed Shift Technology

IA Core Level 1 and Level 2 Caches Intel® Speed Shift Technology