Jasper Lake EDS Vol1

Datasheet

ID 633935
Date 01/01/2021
Public Content

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Document Table of Contents
DSP

Memory Specifications

DDR4 DC Specification

Symbol

Parameter

Minimum

Typical

Maximum

Units

Notes 1

VIL

Input Low Voltage

0.75*VDDQ

0.68*VDDQ

V

2, 3, 4

VIH

Input High Voltage

0.82*VDDQ

0.75*VDDQ

V

2, 3, 4

IIL

Input Leakage Current (DQ, CK)

0 V

0.2*Vddq

0.8*Vddq

-

1.1

mA

RON_​UP(DQ)

Data Buffer pull-up Resistance

25

60

Ω

5, 12

RON_​DN(DQ)

Data Buffer pull-down Resistance

26

75

Ω

RODT(DQ)

On-die termination equivalent

resistance for data signals

25

Hi-Z

Ω

6, 12

VODT(DC)

On-die termination DC working

point (driver set to receive mode)

0.7 *VDDQ

0.75*VDDQ

0.8*VDDQ

V

12

RON_​UP(CK)

Clock Buffer pull-up Resistance

25

60

Ω

5,12

RON_​DN(CK)

Clock Buffer pull-down Resistance

25

75

Ω

5,12

RON_​UP(CMD)

Command Buffer pull-up

Resistance

23

50

Ω

5,12

RON_​DN(CMD)

Command Buffer pull-down

Resistance

24

57

Ω

5,12

RON_​UP(CTL)

Control Buffer pull-up Resistance

23

50

Ω

5,12

RON_​DN(CTL)

Control Buffer pull-Down Resistance

24

57

Ω

5,12

RON_​UP

(DDR_​VTT_​CTL)

System Memory Power Gate

Control Buffer Pull-up Resistance

45

125

Ω

RON_​DN

(DDR_​VTT_​CTL)

System Memory Power Gate

Control Buffer Pull- down Resistance

40

130

Ω

DDR0_​VREF_​DQ

DDR_​1_​VREF_​CA

DDR_​0_​VREF_​CA

VREF output voltage

Trainable

VDDQ/2

Trainable

V

DDR_​RCOMP[0]

Command resistance compensation

99

100

101

Ω

8

DDR_​RCOMP[1]

Data resistance compensation

99

100

101

Ω

8

DDR_​RCOMP[2]

ODT resistance compensation

99

100

101

Ω

8

Notes:
  1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency.
  2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
  3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
  4. VIH and VOH may experience excursions above VDDQ.
  5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy).
  6. BIOS power training may change these values significantly based on margin/power trade-off.
  7. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards.
  8. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
  9. DDR_​RCOMP resistance should be provided on the system board with 1% resistors. SM_​RCOMP[x] resistors are to VSS. Values are pre-silicon estimations and are subject to change.
  10. PMC_​DRAM_​RESET_​N must have a maximum of 15 ns rise or fall time over VDDQ * 0.30 ±100 mV and the edge must be monotonic.
  11. DDR_​[1:0]_​VREF_​CA is defined as VDDQ/2 for DDR4/LPDDR4.
  12. RON tolerance is preliminary and might be subject to change.
  13. Max-min range is correct but center point is subject to change during MRC boot training.
  14. Processor may be damaged if VIH exceeds the maximum voltage for extended periods.

LPDDR4/x Memory Controller DC Specification

LPDDR4/x DC Specifications

Symbol

Parameter

Minimum

Typical

Maximum

Units

Notes

VIL

Input Low Voltage

0.2*VDDQ

0.08*VDDQ

V

2, 3, 4

VIH

Input High Voltage

0.35*VDDQ

0.2*VDDQ

V

2, 3, 4

IIL

Input Leakage Current(DQ, CK)

0 V

0.2*VDDQ

0.8*VDDQ

-

1

mA

-

RON_​UP(DQ)

Data Buffer pull-up Resistance

25

(LP4x:23)

60

(LP4x:58)

Ω

5,10

RON_​DN(DQ)

Data Buffer pull-down Resistance

25

(LP4x:26)

72

(LP4x:85)

Ω

5,10

RODT(DQ)

On-die termination equivalent resistance for data signals

28

(LP4x:26)

Hi-Z

Ω

6, 10

VODT(DC)

On-die termination DC working point (driver set to receive mode)

0.15*vddq

(LP4x: 0.25*

VDDQ)

0.2* VDDQ

(LP4x:

0.3*

VDDQ)

0.25*VDDQ

(LP4x:0.35*

VDDQ)

V

10

RON_​UP(CK)

Clock Buffer pull-up Resistance

24

(LP4x:30)

60

(LP4x:59)

Ω

5, 10

RON_​DN(CK)

Clock Buffer pull-down Resistance

28

92

(LP4x:94)

Ω

5, 10

RON_​UP(CMD)

Command Buffer pull-up Resistance

26

50

Ω

5, 10

RON_​DN(CMD)

Command Buffer pull-down Resistance

22

(LP4x:20)

67

Ω

5, 10

RON_​UP(CTL)

Control Buffer pull-up Resistance

26

50

Ω

5, 10

RON_​DN(CTL)

Control Buffer pull-down Resistance

22

(LP4x:20)

67

Ω

5, 10

DDR0_​VREF_​DQ

DDR_​1_​VREF_​CA

DDR_​0_​VREF_​CA

VREF output voltage

Trainable

V

-

DDR_​RCOMP[0]

Command resistance compensation

99

100

101

Ω

8

DDR_​RCOMP[1]

Data resistance compensation

99

100

101

Ω

8

DDR_​RCOMP[2]

ODT resistance compensation

99

100

101

Ω

8

Notes:
  1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency.
  2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
  3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
  4. VIH and VOH may experience excursions above VDDQ.
  5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training may change these values significantly based on margin/power trade-off.
  6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards.
  7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
  8. LP4_​RCOMP resistance should be provided on the system board with 1% resistors. SM_​RCOMP[x] resistors are to VSS. Values are pre-silicon estimations and are subject to change.
  9. PMC_​DRAM_​RESET_​N must have a maximum of 15 ns rise or fall time over VDDQ * 0.30 ±100 mV and the edge must be monotonic.
  10. SM_​VREF is defined as VDDQ/2 for DDR4/LPDDR4.
  11. RON tolerance is preliminary and might be subject to change.
  12. Max-min range is correct but center point is subject to change during MRC boot training.
  13. Processor may be damaged if VIH exceeds the maximum voltage for extended periods.