Jasper Lake EDS Vol1

Datasheet

ID Date Version Classification
633935 01/01/2021 Public Content

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Document Table of Contents
DSP

Signal Description

Signal Descriptions

Name

Type

Description

Intel® High Definition Audio Signals

GP_​R04/HDA_​RST_​N

O

Intel® HD Audio Reset: Master H/W reset to internal/external codecs.

GP_​R01/HDA_​SYNC/AVS_​I2S0_​SFRM

O

Intel® HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. Also used to encode the stream number.

GP_​R00/HDA_​BCLK/AVS_​I2S0_​SCLK

O

Intel® HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel® HD Audio controller.

GP_​R02/HDA_​SDO/AVS_​I2S0_​TXD

O

Intel® HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s.

GP_​R03/HDA_​SDI0/AVS_​I2S0_​RXD

I

Intel® HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered.

GP_​R05/HDA_​SDI1/AVS_​I2S1_​RXD

I

Intel® HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered.

I2S/PCM Interface

GP_​R00/HDA_​BCLK/AVS_​I2S0_​SCLK

I/O

I2S/PCM serial bit clock 0: Clock used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​H15/AVS_​I2S1_​SCLK

I/O

I2S/PCM serial bit clock 1: This clock is used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​H11/AVS_​I2S2_​SCLK

I/O

I2S/PCM serial bit clock 2: This clock is used to control the timing of a transfer. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​R01/HDA_​SYNC/AVS_​I2S0_​SFRM

I/O

I2S/PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​R06/AVS_​I2S1_​SFRM

I/O

I2S/PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​H12/AVS_​I2S2_​SFRM/CNV_​RF_​RESET_​N

I/O

I2S/PCM serial frame indicator 2: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Master mode) or taken from an external source (Slave mode).

GP_​R02/HDA_​SDO/AVS_​I2S0_​TXD

O

I2S/PCM transmit data (serial data out)0: This signal transmits serialized data. The sample length is a function of the selected serial data sample size.

GP_​R07/AVS_​I2S1_​TXD

O

I2S/PCM transmit data (serial data out)1: This signal transmits serialized data. The sample length is a function of the selected serial data sample size.

GP_​H13/AVS_​I2S2_​TXD/MODEM_​CLKREQ

O

I2S/PCM transmit data (serial data out)2: This signal transmits serialized data. The sample length is a function of the selected serial data sample size.

GP_​R03/HDA_​SDI0/AVS_​I2S0_​RXD

I

I2S/PCM receive data (serial data in)0: This signal receives serialized data. The sample length is a function of the selected serial data sample size.

GP_​R05/HDA_​SDI1/AVS_​I2S1_​RXD

I

I2S/PCM receive data (serial data in)1: This signal receives serialized data. The sample length is a function of the selected serial data sample size.

GP_​H14/AVS_​I2S2_​RXD

I

I2S/PCM receive data (serial data in)2: This signal receives serialized data. The sample length is a function of the selected serial data sample size.

GP_​D18/AVS_​I2S_​MCLK

O

I2S/PCM Master reference clock: This signal is the master reference clock that connects to an audio codec.

DMIC Interface

GP_​S06/DMIC_​CLK_​0

O

Digital Mic Clock: Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz.

GP_​S02/DMIC_​CLK_​1

O

Digital Mic Clock: Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz.

GP_​S07/DMIC_​DATA_​0

I

Digital Mic Data: Serial data input from the digital mic.

GP_​S03/DMIC_​DATA_​1

I

Digital Mic Data: Serial data input from the digital mic.

SoundWire* Interface

GP_​S04/SNDW1_​CLK

I/O

SoundWire* Clock: Serial data clock to external peripheral devices.

GP_​S05/SNDW1_​DATA

I/O

SoundWire* Data: Serial data input from external peripheral devices.