CPU_​JTAG_​TCK

IN

Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic

PCH_​JTAG_​X

IN

Pin used to support Merged Debug Port topology

CPU_​JTAG_​TMS

PCH_​JTAG_​TMS

IN

Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations

CPU_​JTAG_​TDI

PCH_​JTAG_​TDI

IN

Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI

CPU_​JTAG_​TDO

PCH_​JTAG_​TDO

OUT

Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard

CPU_​JTAG_​TRST_​N

PCH_​JTAG_​TRST_​N

IN

Test Reset (active low)

DBG_​PMODE²

IN/OUT

Debug Power Mode Indicator. Signal is used to transmit Compute Die and PCH power/reset information to the debug tool

CFG[00:15]³

IN/OUT

CFG (Parallel Trace Interface) signals are used for Compute Die Tracing