Jasper Lake EDS Vol1
Closed Chassis Debug
Closed Chassis Debug is a means to allow access to the JTAG and trace via an external interface, ordinarily a USB connector. It used Intel® DCI technologies. There are two types of Intel® DCI hosting interfaces in the platform. Intel® DCI is implemented using two primary transport topologies:
- Intel® Direct Connect Interface Out of Band (DCI.OOB, formerly BSSB)
- Intel® DCI.USB2 and DCI.USB3 (formerly DbC)
In the beginning of Early-Boot Debug, an Open and Closed-Chassis Debug are required. Both JTAG (Open Chassis) and DCI.OOB (Closed Chassis) are available prior the first Platform Boot Stall. Intel® DCI.USB2 becomes available which enables before CSE Boot Stall. Then Intel® DCI.USB3 is available during in S0 power state.
Intel® System Studio is a Software tools suite for System and IoT Development. Further information on how to run Intel® DCI through Intel® System Studio System is available at https://software.intel.com/en-us/articles/system-debugging-via-direct-connect-interfacedci-of-intel-system-debug. It can be used to run Intel® DCI by using its component tool called Intel® System Debugger. More information about Intel® System Studio is available at https://software.intel.com/en-us/system-studio.
In summary, Intel® DCI supports capabilities as below:
- Closed Chassis Debug at S0 and Sx State
- JTAG Access and Run-control (Probe Mode)
- System Tracing with Intel® Trace Hub
Debug host software that support Intel® DCI is:
- Intel® System Studio (ISS)
- TRACE32 by Lauterbach
Intel® DCI.OOB (Out of Band)
Intel® DCI.OOB was developed to provide an alternate path to convey controls and data to or from Intel® Trace Hub by connecting physically to the target through a USB 3.1 Gen2 port over Type A receptacle. Intel® DCI.OOB provides an alternate side band path around the USB 3.1 controller, so that the embedded logic can be accessed, even when the USB 3.1 controller is not alive (such as in low power states) or is malfunctioning. This path does not rely on USB 3.1 Gen2 protocol, link layer, or physical layer, because the xHCI functions are generally not available in such conditions.
Instead, this path relies on a special adapter that was developed by Intel called Intel® SVT Closed Chassis Adapter (CCA). It is a simple data transformation device. This adapter works together with debug host software and the embedded logic, contain a back-pressure scheme that makes both sides tolerant of overflow and starvation conditions, which is equivalent of USB 3.1 Gen2 link layer. This path also use native Intel® DCI packet protocol instead of USB 3.1 Gen2 protocol.
Intel® SVT CCA (MM Number: 921521) can be purchased through Intel® Design-In Tools Store at https://designintools.intel.com/product_p/itpxdpsvt.htm.
Besides Intel® SVT CCA, Lauterbach is an example of Third Party Vendor (TPV) solution. User may use a specific Lauterbach hardware and software configuration to connect between the Debug Host System and the Target Platform. It need Debug Host System (Lauterbach CombiProbe) to be in Downstream Facing Port (DFP) mode for Intel® DCI.OOB support in S0ix and Debug Host System (Lauterbach CombiProbe) can be DFP or Upstream Facing Port (UFP) for Intel® DCI.OOB supports in S0. Intel® SVT CCA (MM#:921521) can be purchased through Intel® Design-In Tools Store at https://designintools.intel.com/product_p/itpxdpsvt.htm.
Intel® DCI.USB2 and DCI.USB3
Intel® DCI USB2 and DCI.USB3 is a USB hosted Intel® DCI transport and the higher USB bandwidths, multiple parallel pipes or endpoints and BULK-mode data-integrity and retry-recovery mechanisms built into the protocol.
- DFx for JTAG/Run-control IA cores in system
- General Purpose 1 (GP1) for Kernel Mode Debug (KMD)
- General Purpose 2 (GP2) for Direct Memory Access (DMA) to system memory
- Trace (TRC) for streaming of live tracker
- Intel® DCI.USB2 - Provides limited ~35 MB/s usable bandwidth, but extends USB hosting to cover early-boot and low power Sx and S0ix states.
- Intel® DCI.USB3 - Provides an increase in S0 bandwidth up to ~800 MB/s usable bandwidth (generally limited further by host and host SW).