The PECI interface operates at a nominal voltage set by VccST. The set of DC electrical specifications shown in the following table is used with devices normally operating from a VccST interface supply.
VccST nominal levels will vary between processor families. All PECI devices will operate at the VccST level determined by the processor installed in the system.
Note: PECI supported frequency range is 3.2 KHz - 1 MHz
PECI DC Electrical Limits
Associated Signal: PECI
Definition and Conditions
Internal pull up resistance
Input Voltage Range
Vcc + 0.15
0.15 * Vcc
Input Voltage Low- Edge Threshold Voltage
0.3 * Vcc
Input Voltage High- Edge Threshold Voltage
0.7 * Vcc
Bus Capacitance per Node
VccST supplies the PECI interface. PECI behavior does not affect VccST min/max specifications.
The leakage specification applies to powered devices on the PECI bus.
The PECI buffer internal pull up resistance measured at 0.75* VccST.
Input Device Hysteresis
The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design.